RTL Design / Microarchitecture Engineer

Bolt Graphics•Sunnyvale, CA

22h•$160,000 - $220,000

About The Position

As an RTL Design / Microarchitecture Engineer, you will define and implement key microarchitectural components of our SoC/IP. You will work closely with architecture, verification, and physical design teams to deliver high-performance, scalable, and power-efficient designs.

Requirements

Bachelor’s/Master’s degree in Electrical Engineering or related field
5–10 years of experience in RTL design and microarchitecture
Strong expertise in: RTL design using SystemVerilog/Verilog
Microarchitecture development for complex digital systems
Performance optimization and pipelining techniques
Experience with simulation and debugging tools such as: Synopsys VCS / Cadence Xcelium
Familiarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)
Strong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces)
Experience working in ASIC/SoC development environments

Nice To Haves

Experience in one or more domains: CPU, GPU, AI/ML accelerators, networking, or high-speed data processing
Knowledge of memory subsystem design (SRAM, cache hierarchies, coherency)
Familiarity with low-power design techniques (clock gating, power domains)
Exposure to formal verification or linting tools
Experience with GLS, SDF annotation, and silicon debug
Scripting skills (Python/TCL) for automation
Understanding of hardware-software interaction (firmware, drivers)

Responsibilities

Define and develop microarchitecture specifications from high-level architecture requirements
Design and implement RTL (SystemVerilog/Verilog) for complex digital blocks
Drive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level
Collaborate with verification teams to ensure high coverage and design correctness
Support integration of IPs into SoC-level environments
Work with physical design teams for timing closure, synthesis constraints, and floorplan-aware design
Debug and resolve issues during simulation, GLS, and silicon bring-up
Participate in design reviews, architecture discussions, and cross-functional planning
Contribute to design documentation and methodology improvements