RTL Design Engineer, Silicon

Google•Mountain View, CA

3h•$138,000 - $197,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience with IP development or integration.
Experience in ASIC development with Verilog or VHDL.
Experience with a scripting language like Perl or Python.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
Knowledge of high-performance and energy efficient design techniques.
Knowledge of FPGA and emulation platforms.
Knowledge of ASIC Verification or DFT.

Responsibilities

Define microarchitecture for a subsystem.
Integrate internal and/or external IP.
Define microarchitecture of a small to medium size IP.
Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in test plan and coverage analysis of the sub-system and chip-level verification.