RFIC Layout Designer (RFIC Engineering)

SpaceX • Irvine, CA

27d

About The Position

SpaceX is seeking motivated, proactive, and intellectually curious engineers to join their RFIC Engineering team. This role involves working on multiple silicon projects focused on increased integration, lower power, mixed-signal architectures, and advanced silicon technology for space and ground infrastructure. The RFIC Layout Designer will be an integral part of the IC design team, leading the layout discipline at a technical level and collaborating with RFIC/mixed-signal designers on full-chip layout of custom analog and RFIC designs.

Requirements

• Bachelor’s degree in electrical or computer engineering and 1+ years of professional experience as an IC layout designer; OR 3+ years of professional experience with integrated circuit layout design in lieu of a degree.
• Must be willing to work extended hours and weekends as needed to meet critical milestones.
• Must be a U.S. citizen or national, U.S. lawful, permanent resident, Refugee, or Asylee, or eligible to obtain required U.S. Department of State authorizations.

Nice To Haves

• Strong analog layout skills.
• Experience in advanced node IC layouts (e.g., 22nm, 16nm, 7nm, 5nm or below).
• Experience in layout of circuits with frequencies up to 50GHz.
• Experience in layout of sensitive RF blocks (e.g., low noise amplifiers, voltage controlled oscillators, mixers).
• Experience with skill programming.
• Experience with shell scripting, Perl, Python, or similar languages.
• Experience managing revision control systems.
• Experience with circuit design.
• Understanding of layout considerations for device matching, coupling, and noise isolation.
• Working knowledge of Linux.
• Excellent communication skills (both oral and written).
• Able to work independently on challenging problems.

Responsibilities

• Work with integrated circuit designers and chip leads to determine the chip floor plan, including strategies for power and ground distribution and pad locations in collaboration with packaging engineers.
• Accurately estimate the schedule for layout work and identify areas of complexity requiring early investigation.
• Perform layout of custom RF and analog circuit blocks, focusing on matching and minimizing parasitic capacitance.
• Conduct design rule checking, electrical rule checking, and layout versus schematic checks, and resolve any errors.
• Perform top-level layout integration, including electrostatic discharge structures and pad assembly, and execute final tape-out (density fill, manufacturability checks, and GDS sharing with the foundry).
• Collaborate with EDA suppliers to evaluate new tools and features.
• Generate guides and demonstrations for team members to share improvements in layout techniques.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level