Member of Technical Staff, Reliability Engineer

Lumotive•Redmond, WA

9d•$90,000 - $105,000

About The Position

Lumotive is pioneering the era of programmable optics, controlling light as intelligently and flexibly as software. At the core of this innovation is a flat CMOS-based 'general purpose optic' called the Light Control Metasurface (LCM™). This chip can be programmed for various optical functions, replacing bulky mechanical components with a digital, reconfigurable semiconductor. This breakthrough is set to reshape industries like 3D sensing, imaging, optical networking, and free space optical communication, impacting robotics, self-driving cars, AI, defense, and healthcare. Lumotive's initial application is in LiDAR, where its software-defined beam steering chips enable compact, high-performance, solid-state sensors deployed in smart infrastructure, robotics, and mobility systems. With over 200 patents and growing commercial traction, Lumotive is delivering the world's first digital platform for light. This role focuses on owning the reliability of the LCM chip, a novel semiconductor device combining a CMOS backplane, thin-film material stacks, and liquid crystal. This position requires a deep, first-principles understanding of LCM failure modes, which may extend beyond standard CMOS reliability. The engineer will design and execute accelerated stress tests, perform hands-on failure analysis, build lifetime models, and correlate reliability outcomes with manufacturing processes. A key aspect of this role is anticipating future failure modes in new use conditions to inform the team of risks early, directly influencing process, design, and materials decisions to accelerate high-volume production.

Requirements

Bachelor’s degree in electrical engineering, physics, materials science, or related fields is required.
Minimum of 5 years of experience in semiconductor or optoelectronic device reliability, failure analysis, or closely related roles is required.
Hands-on experience designing and executing accelerated stress tests (e.g., HTOL, temperature cycling, humidity / HAST, high temperature storage).
Hands-on failure analysis experience: optical microscopy, electrical characterization, and systematic root-cause investigation.
Statistical reliability analysis skills: time-to-failure distributions (e.g., Weibull), acceleration modeling (e.g., Arrhenius), and lifetime projection.
Demonstrated experience characterizing failure modes that fall outside standard textbook models — working them from first principles rather than relying solely on established qual flows.
Proficiency in Python, JMP, or similar for data analysis of large reliability datasets.
Strong written and verbal communication skills; disciplined about documenting work with clear conclusions and next steps.
Intellectual curiosity and ownership: you think about what can fail constantly, and you dig until you understand why.

Nice To Haves

A Master’s or PhD is preferred.
Background in liquid crystal devices (LCoS, displays), MEMS, image sensors, photonics, or other emerging semiconductor device technologies.
Familiarity with reliability and quality standards (JEDEC, AEC-Q100) and how to adapt them to devices they were not written for.
Experience running split-lot design-of-experiments with wafer fabs or materials vendors to improve reliability.
Experience defining burn-in and production screening for early-failure elimination.
Experience with test data infrastructure: databases, Tableau or similar dashboards, Git and software development best practices.

Responsibilities

Own core LCM reliability at the chip level: define the stress test strategy, execute it, and be the authority on LCM failure modes, mechanisms, and lifetime
Design and run accelerated life tests (HTOL, high temperature storage, temperature cycling, humidity / biased-humidity, optical exposure) and define new stress conditions that surface latent failure modes early
Perform hands-on failure analysis: optical and electrical inspection, defect tracking and precursor identification, root-cause hypothesis generation and testing
Build statistical lifetime models (time-to-failure distributions, acceleration factors, activation energies) to project reliability from accelerated conditions to customer use conditions
Correlate reliability outcomes with wafer fab process splits, materials experiments, and assembly variables; drive design-of-experiments with process and fab partners to improve intrinsic reliability
Define pass / fail criteria, burn-in, and screening strategies to keep early failures out of customer deliveries
Develop and maintain the analysis tooling (Python, test databases, dashboards) that turns raw stress-test data into conclusions
Communicate findings rapidly and clearly: document every study in our knowledge base with conclusions and next steps, present at reliability reviews, and flag new failure modes to the broader team the day you find them