R&D Technical Project Manager-Vector Network Analysis

Keysight Technologies, Inc.•Santa Rosa, CA

13h•Onsite

About The Position

Keysight drives innovation in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees build world‑class solutions across communications, 5G/6G, automotive, energy, quantum, aerospace, defense, and semiconductor markets in more than 100 countries. Our award‑winning culture embraces bold ideas, technical rigor, and a passion for solving hard problems with industry‑first solutions. We believe belonging empowers people to innovate and thrive throughout their careers. About the Job This role leads the execution of the Labs technology portfolio that powers Keysight’s VNA product roadmap—spanning MMICs, SiPs, and subsystems. You will run a single PLC across Labs technologies (NCI, NSI, Subsystems) from CON to SHP, giving leadership a clear view of investment, schedule, dependencies, and realized ROI into NPIs. You’ll align deliverables with Centers of Excellence (CoEs) and Solutions Groups, orchestrate fab priority with the Labs Materials Planner (in concert with PICO and PMTC), and drive resourcing tradeoffs with other TPMs and Technology Managers. You’ll partner with product and research leaders to capture future requirements, compare proposals to next‑best commercial alternatives, make data‑driven investment recommendations, and market Labs parts for maximal reuse and ROI across multiple product lines. About the Team You will join the Signal Conditioning and Subsystems section in Keysight Labs. The team builds analog and mm‑wave front ends (ICs + modules) for VNA platforms and frequency-domain applications, collaborating closely with CoEs and Industry Solutions Groups.

Requirements

B.S./M.S./Ph.D. in Electrical Engineering or related field with 5–10+ years of applicable experience in analog/mm‑wave ICs, SiPs, and related packaging/subsystem technologies.
1–5+ years in technical project/program management for new technologies and NPIs (or Team Lead roles with equivalent scope).
Strong communicator with a track record of instilling customer confidence and aligning diverse stakeholders.
Broad knowledge of electronic systems, especially high‑frequency analog/RF/mmWave and VNA‑relevant subsystems.
General understanding of semiconductor foundry operations, including Keysight HFTC and external partners.
Demonstrated ability to make decisions, take initiative, drive to results, and collaborate in fast‑paced environments.

Nice To Haves

Experience orchestrating fab priorities, materials planning, and E2E build/test flows for MMICs/SiPs/subsystems.
Familiarity with PLC gating, NPI governance, and tools such as Jira/Confluence, MS Project/Smartsheet, Power BI/Excel.
Background working with CoEs/Solutions Groups and external customers on requirements and productization.
Understanding of reliability/qualification considerations for RF/mmWave components and modules.

Responsibilities

Portfolio & PLC Governance (CON → SHP)
Run a single PLC across Labs technologies (NCI, NSI, Subsystems) that feed VNA NPIs; maintain a unified, auditable view of scope, cost, schedule, risk, and benefits.
Define and track gate criteria and closure plans; ensure cross‑functional readiness for each PLC gate.
Maintain a concise executive dashboard highlighting status, deltas, critical risks, dependencies, and ROI realization.
Planning & Execution
Run regular project meetings (with IC, SIP and subsystem attendees together) and track progress from all contributors, raising and resolving any technical/non-technical issue appropriately
Align with CoEs on NCI/NSI/Subsystem deliverables (scope, schedule, acceptance criteria) tied to NPI milestones.
Sequence/coordinate fab runs and builds with the Labs Materials Planner; ensure end‑to-end priority alignment with PICO and PMTC.
Manage integration plans for MMICs, SiPs, and subsystems into VNA architectures, including validation and qualification dependencies.
Resourcing, Risk & Dependency Management
Partner with Labs TPMs and Technology Managers to broker staffing tradeoffs and resolve bottlenecks.
Drive proactive risk identification/mitigation (supply, process, yield, packaging, test throughput, firmware dependencies).
Maintain what‑if scenarios for critical paths and long-lead items (masks, substrates, specialized materials, fixtures).
Requirements & Roadmapping
Meet regularly with CoE and IST PMs/planners: capture future requirements (performance, cost, reliability, manufacturability) for ICs, SiPs, subsystems; translate into capability roadmaps.
Partner with design leads and architects to balance performance vs. cost vs. schedule; validate feasibility against fab and assembly/test constraints.
Stakeholder Communication
Provide regular program updates to Labs senior management, with sharp narratives and decision asks.
Keep customer/partner divisions synchronized on progress and risks.
Technical Context (VNA‑Focused)
Manage building blocks typical of VNA front ends and frequency‑domain chains (e.g., mixers, LNAs/PAs, T/R modules, couplers/attenuators/switches, LO distribution, frequency extenders, calibration and metrology modules, multi‑chip SiPs, and integrated subsystems).
Ensure test strategies and DVT/qualification align with VNA performance targets, including stability, linearity, noise, dynamic range, and calibration integrity.