R&D IC Design Engineer

Broadcom•San Jose, CA

About The Position

This opening works on chip design which enables 10Gbps/40Gbps/100Gbps/400Gbps backplane/cable/optical fiber communication. The role involves architecting block level design specifications from marketing and/or system requirements, preparing detailed design documents, and HDL coding. Responsibilities include equivalency checking, STA result review, CDC checks, Lint checks, RTL/gate level simulations, silicon debugging, and scripting for various IC design tasks. The engineer will also prepare block level resource requirements and development schedules, generate verification and test plans, perform design tradeoff analysis (leakage, dynamic power, die size, schedule, resource, priority), and be involved in silicon bring-up.

Requirements

B.S degree in EE or computer Engineering. Minimum of 12 years of work experience with direct related technical skill
M.S degree/Ph.D in EE or Computer Engineering with 10 years of work experience.
Good knowledge of ARM subsystem
Good knowledge of high speed digital circuit design.
Good knowledge of 10G/100G Ethernet and OTN network
Strong analytical and problem solving skills as well as hands-on lab debugging experiences
Good knowledge of RTL simulation and synthesis.
In-depth knowledge for design for low power and design for test and design for manufacturing.
Good Knowledge in languages relevant to the ASIC development process including Verilog, VHDL, Unix/Perl Scripting or Python, and C.
Self-motivated, excellent communication skills and ability to excel in a team environment.
Good organization skills, able to follow through & bring issue to closure
Understand the entire IC development flow & procedure including silicon volume production qualification requirements & procedures
Enthusiastic & enjoy IC development works
Be able to work with teams at remote locations with different time zones.

Nice To Haves

Good knowledge of digital signal processing and error correction code is a plus
Experience with High-level Synthesis in design and verification is a plus.
DSP design knowledge is a plus
Knowledge Backplane/cable/optical fiber communication is a plus

Responsibilities

Architect block level design specifications from the marketing requirements and/or system requirements
Prepare detailed design document, timing constraint file
HDL coding, equivalency checking, STA result review, CDC checks, Lint checks, RTL/gate level simulations & silicon debugging
Scripting for various IC design tasks such as STA, equivalency checks, test bench, simulations, synthesis, etc.
Prepare block level resource requirements & development schedule
Generate verification & test plans for design validation
Perform design tradeoff analysis – leakage, dynamic power, die size, schedule, resource, priority, etc.
Silicon bring up