R&D Engineering Scientist

Synopsys•Sunnyvale, CA

52d•$244,000 - $366,000•Onsite

About The Position

At Synopsys, the R&D Engineering Scientist will architect advanced high-speed PHY and SerDes IP, translating protocol, channel, and system requirements into implementable architectures while balancing power, performance, area, latency, and reliability. The role focuses on 112 Gb/s and 224 Gb/s PAM4 PHY architectures and works across analog, digital, signal-integrity, package, program, and customer-facing teams. The scientist will define data-path and clocking architectures, calibration and adaptation strategies, component-level PPA and latency allocations, block specifications, end-to-end link budgets, and architecture sign-off and silicon bring-up requirements. The role contributes to first-silicon success, reduces integration risk through cross-functional specifications and sign-off criteria, and enables differentiated high-performance interface IP for advanced silicon applications. The position is part of a multidisciplinary team developing advanced high-speed PHY IP, collaborating with analog, digital, verification, signal-integrity, power-integrity, package, and silicon-validation teams. The position is based in Sunnyvale, California, and is not remote eligible.

Requirements

Strong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links.
Expertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.
Deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration.
Experience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.
Silicon bring-up and debug experience using PRBS, loopback, eye scan, and calibration capabilities.
Ability to write clear technical specifications and explain architecture decisions to technical, program, and customer audiences.
Ability to collaborate across disciplines and geographies and translate complex tradeoffs into actionable decisions.

Responsibilities

Own PHY architecture, including protocols, data rates, BER, and PPA targets.
Define data-path and clocking architectures, including modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.
Lead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.
Allocate power, area, performance, and latency across analog, digital, and package components.
Develop block specifications for engineering implementation and verification.
Close the end-to-end link budget across the transmitter, package, channel, and receiver.
Define architecture sign-off, modeling, observability, and silicon bring-up requirements, including loopback, PRBS, eye scan, and calibration access.
Align standards, signal-integrity, power-integrity, package, and program teams on guaranteed IP performance.
Define advanced 112 Gb/s and 224 Gb/s PAM4 PHY architectures.
Improve first-silicon success through link budgeting, modeling, and observability.
Reduce integration risk by establishing cross-functional specifications and sign-off criteria.
Enable differentiated, high-performance interface IP for advanced silicon applications.