R&D Engineering, Director-18881

Synopsys•Sunnyvale, CA

13d•$230,000 - $344,000•Onsite

About The Position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technologies enable the world's most advanced semiconductor companies to develop differentiated products across AI, automotive, hyperscale computing, networking, and mobile markets. As complexity grows, ensuring product quality, reliability, and manufacturability has never been more critical. The Digital Methodology Center of Excellence (DMCoE) develops and deploys industry-leading methodologies that enable successful adoption of Synopsys TestMAX® solutions and advanced Design-for-Testability technologies across the semiconductor ecosystem. You are a recognized DFT expert with extensive experience architecting and deploying test solutions for complex ASIC and SoC designs. You possess deep knowledge of scan architectures, ATPG, test access infrastructures, and DFT standards, coupled with the ability to influence technical strategies across organizations. You have a proven track record of defining methodologies, driving tool adoption, solving complex customer challenges, and leading cross-functional initiatives. You are equally comfortable discussing DFT architecture with design engineers, manufacturing test strategies with product engineers, and deployment roadmaps with technical leadership. You thrive in highly collaborative environments where innovation, technical excellence, and customer success are paramount. What You'll Be Doing: Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs. Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions. Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies. Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards. Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization. Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units. Collaborate with R&D organizations to influence future product capabilities and roadmap priorities. Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations. Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise. The Impact You Will Have: Enable successful deployment of industry-leading DFT methodologies across the world's most advanced semiconductor programs. Drive measurable improvements in test quality, manufacturability, and silicon reliability. Influence next-generation TestMAX capabilities through direct customer engagement and technical leadership. Accelerate adoption of advanced standards-based test architectures across strategic customer accounts. Improve engineering productivity through methodology standardization, automation, and best-practice development. Establish Synopsys as the trusted advisor and technology leader in DFT and manufacturing test solutions. Contribute to breakthrough technologies powering AI, automotive, networking, and high-performance computing applications. Who You Are: A strategic technical leader capable of influencing engineering direction across organizations. A trusted advisor to customers, partners, and internal stakeholders. An exceptional communicator who can present complex technical concepts to diverse audiences. A mentor who develops talent and elevates the technical capabilities of those around them. An innovator who continuously seeks opportunities to improve methodologies, tools, and customer outcomes. Results-driven, highly collaborative, and passionate about solving the industry's most challenging DFT problems. The Team You'll Be A Part Of: You will join the Digital Methodology Center of Excellence, a highly visible organization responsible for defining and advancing Synopsys' DFT methodologies, best practices, and customer deployment strategies. Working closely with R&D, product engineering, customer success, and strategic accounts, you will help shape the future of Design-for-Test and drive successful adoption of the industry's most advanced test solutions worldwide. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or related field.
15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
Strong understanding of: Scan insertion and scan compression, Hierarchical DFT methodologies, ATPG and diagnosis, Stuck-at, transition, path-delay, bridge, and cell-aware fault models, Coverage analysis and optimization, Test cost and pattern count reduction techniques.
Expertise with standards including: IEEE 1149.1 (JTAG), IEEE 1149.6 (AC JTAG), IEEE 1687 (IJTAG), IEEE 1500.
Experience developing and deploying: JTAG / TAP Architectures, Boundary Scan Networks, IJTAG Instrumentation Networks, Embedded Instrument Access Solutions.
Expertise in deploying and integrating DFT IP including: Codec / Embedded Compression, OCC (On-Chip Clock Controller), LBIST, TAP Controllers, JTAG and IJTAG Infrastructure, TDR Networks, IEEE 1500 Wrappers.
Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.

Nice To Haves

Recognized expert in DFT architecture and test methodology deployment.
Experience defining enterprise-wide DFT standards and signoff methodologies.
Strong background supporting advanced-node ASICs and multi-billion gate SoCs.
Experience with silicon bring-up, diagnosis, yield improvement, and production ramp.
Knowledge of functional safety standards and test requirements for automotive applications.
Experience collaborating directly with semiconductor customers in applications engineering, consulting, or methodology leadership roles.
Contributions to industry test standards, technical publications, patents, or conference presentations are highly valued.

Responsibilities

Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
Serve as a technical leader and subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
Collaborate with R&D organizations to influence future product capabilities and roadmap priorities.
Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
Mentor engineers across multiple teams and contribute to the development of the organization's DFT expertise.