R&D DSP/FPGA Design Automation Intern

Keysight Technologies, Inc.•Santa Rosa, CA

About The Position

Keysight is seeking a motivated R&D intern to help develop and demonstrate a scalable, AI-assisted development workflow for FPGA-based digital signal processing systems. The role suits a student interested in combining signal processing, digital design, and software development. The intern will gain experience across the FPGA development lifecycle and investigate how AI-assisted engineering can improve development speed, reuse, and consistency while maintaining sound engineering judgment.

Requirements

Currently pursuing a Bachelor's or Master's degree in EE, CE, CS, or a related field.
Coursework, project work, or job experience in DSP or digital system design.
Understanding of digital logic, synchronous design, pipelining, and FSMs.
Experience with at least one HDL or hardware-construction language, such as Verilog, SystemVerilog, VHDL, or Chisel.
Experience with Python, MATLAB, C/C++, or a similar language for modeling or automation.
Familiarity with fixed-point arithmetic, quantization, or numerical implementation of DSP algorithms.
Ability to turn requirements into an implementable design.
Ability to analyze technical results and communicate conclusions clearly.
Strong problem-solving, communication, and teamwork skills.
Ability and desire to learn emerging technologies.

Nice To Haves

Experience designing, simulating, or synthesizing FPGA logic with Xilinx/AMD, Intel, or comparable tools.
Experience with streaming interfaces such as valid/ready, FIFOs, or clock domains.
Experience implementing FIR filters, resamplers, channelizers, or other waveform processing.
Experience writing parameterized, reusable HDL.
Experience with cocotb, constrained-random testing, assertions, or formal verification.
Experience with Git, CI, automated builds, or regression testing.
Experience building software tools for other engineers.
Experience using AI-assisted tools for software, HDL, testing, or analysis.
Familiarity with component metadata, interface contracts, model-based design, or digital twins.
Interest in FPGA tradeoffs among throughput, latency, timing, and DSP, memory, and logic resources.

Responsibilities

Build reusable, parameterized FPGA components for DSP, including MACs, FIFOs, adder trees, coefficient memories, delay elements, and numeric conversion blocks.
Translate DSP and system requirements into FPGA architecture and implementation specifications.
Design and verify RTL in Verilog, SystemVerilog, VHDL, or an equivalent language.
Write bit-accurate or fixed-point reference models to check FPGA implementations.
Assemble components into a representative streaming DSP subsystem.
Create automated simulation and verification tests covering numerical accuracy, reset behavior, streaming interfaces, backpressure, and parameter boundaries.
Support synthesis, timing analysis, resource evaluation, and optimization.
Use Python or a similar language to automate design, testing, data collection, and reporting.
Investigate AI-assisted development tools for FPGA architecture, implementation, verification, and documentation, and define objective ways to measure their output quality.
Analyze results and identify functional, numerical, timing, or resource limitations.
Collaborate with DSP, FPGA, software, and system engineers, including in design reviews.
Document interfaces, parameter constraints, verification results, and findings.
Present results and recommendations to the engineering team at the end of the internship.