Quantum Topological Qubit Integration

GlobalFoundries•Essex Junction, VT

1d•$85,000 - $146,000

About The Position

The Topological Qubit Integration (Principal Engineer) role is a key technical contributor within the Quantum Technology Solutions organization focused on enabling scalable topological quantum computing platforms. This position supports the integration of advanced materials, device architectures, and semiconductor process technologies required for topological qubits, bridging emerging device concepts with manufacturable semiconductor solutions. This role works closely with integration leadership and cross-functional teams to translate quantum device requirements into practical, scalable process integration schemes aligned with performance, yield, and reliability targets.

Requirements

BS or MS in Electrical Engineering, Physics, Materials Science, or related field
5+ years of experience in semiconductor process or integration engineering
Experience with semiconductor device physics and materials interactions
Familiarity with advanced materials systems (e.g., III‑V semiconductors, superconductors, or related materials)
Experience analyzing electrical or physical characterization data
Strong analytical, problem-solving, and debugging skills
Effective communication skills

Nice To Haves

Experience with epitaxial growth or III‑V heterostructures (e.g., MBE, MOCVD)
Background in superconducting or hybrid semiconductor devices
Familiarity with topological quantum devices or related research areas
Experience with BEOL integration, interconnect technologies, or packaging
Experience with cryogenic device behavior and measurements.
Experience with DOE methodologies, yield analysis, or variability modeling
Experience working in advanced R&D or emerging technology environments

Responsibilities

Support integration of topological quantum devices, including III‑V heterostructures, superconducting materials, and hybrid material systems
Develop and execute process integration flows across device modules, BEOL interconnect, and heterogeneous integration schemes
Work with epitaxy and materials teams to ensure integration of III‑V layers, superconductors, and interfaces meets device performance requirements
Contribute to integration of device architectures supporting qubit operation as well as cryogenic read-out and control circuitry
Analyze device and process interactions, including defectivity, variability, contamination, and interface quality
Execute DOE (Design of Experiments) and analyze electrical and physical characterization data to guide process optimization
Support development of superconducting interconnect and low-loss BEOL wiring for operation at cryogenic temperatures
Collaborate with device engineering to ensure alignment between device physics requirements (e.g., coherence, noise, thermal performance) and integration
Participate in yield-learning activities, including root-cause analysis and corrective action implementation
Contribute to definition and tracking of technical milestones, including performance, variability, and reliability metrics
Work cross-functionally with process, materials, packaging, and design enablement teams to ensure successful end-to-end integration
Document integration flows, assumptions, and technical learnings to support scalable development and knowledge transfer
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.