Product Test Engineer

Texas Instruments•Lehi, UT

5d•Onsite

About The Position

Texas Instruments (TI) is seeking a full-time Product Test Engineer (Production) in Lehi, Utah to help ensure manufactured components and assembled products meet company standards and objectives. This role involves developing and implementing testing and evaluation methods, creating test plans, and ensuring products meet electrical and reliability specifications.

Requirements

PhD in Electrical Engineering and one graduate level university internship involving parametric testing and wafer level reliability.
OR Master’s degree in Electrical Engineering and 3 years of experience in semiconductor process flow and device physics or device testing.
Experience to include: 2 years in programming/scripting using either Perl, C/C++, Python, or C#
1 year working in Linux/Unix environment
1 year using Data Analysis tools to discover statistical significance of electrical data sets.

Responsibilities

Develop and implement testing and evaluation methods and create test plans based on production specifications and requirements.
Define and execute the parametric test plan for qualifying new products or technologies, ensuring they meet electrical and reliability specifications.
Perform testing and compiling and analyzing data for review and identification of manufacturing and production issues.
Development of test programs for Parametric and WLR using Keysight tester.
Development, maintenance and troubleshooting of algorithms to support PCD tests for different technologies.
Plan for param test capacity and executing test time reduction.
Keep current on equipment manufacturers' technical notices, upgrades and safety issues.
Study equipment performance and reliability.
Establish programs and solutions for increasing uptime and for equipment problems that affect the manufacturing process.
Provide technical support to Test area manufacturing teams, process engineering and process integration organizations.
Developing and refining test methodologies and parameter extraction routines to capture the physical phenomena affecting memory operation.
Use statistical methods to analyze the variation of key transistor parameters across the wafer and lot.
Improve cross wafer/cross lot variation.
Collaborate with device and layout engineers providing feedback on issues and characterization of specific scribe structures.
Create and implement advanced stress-test algorithms and test routines to accelerate device degradation and characterize specific failure mechanisms such as NBTI, PBTI, TDDB, and Hot Carrier Injection (HCI).
Partner with failure analysis teams to connect parametric shifts during reliability stress with physical failure modes, such as gate oxide breakdown or interconnect migration.
Use dedicated scribe structures to run reliability monitors that provide early warning of shifts in the fabrication process that could impact product lifespan.
Possess programming skills (e.g., C++, Python, Perl) to develop and debug test programs that run on various Automated Test Equipment (ATE) platforms.
Conduct rigorous test correlation and data validation studies to ensure that a test program and its results are equivalent when moved between different hardware configurations or sites.