Product Engineer, Silicon Validation

Etched • San Jose, CA

2d • Onsite

About The Position

We are seeking an experienced Product Engineer to lead silicon validation, test program development, and productization for our large-format AI accelerator chips. In this role, you will develop and execute test strategies from first silicon through high-volume manufacturing, partnering with cross-functional teams and external vendors to ensure production quality and cost targets. This role is critical to achieving first-pass silicon success and seamless NPI-to-HVM transitions.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 5-10+ years of hands-on experience in silicon validation, product engineering, and ATE test development for advanced node semiconductors
• Proven track record in yield optimization and DPPM reduction with quantifiable results
• Experience with silicon characterization methodologies including Fmax/Vmin characterization and power/thermal validation
• High-volume manufacturing test experience with demonstrated production scale results
• Proficiency in yield and fail pareto analysis using JMP, Exensio, DataPower, or OptimalPlus
• Strong understanding of test program debugging, failure analysis correlation, and yield enhancement techniques

Nice To Haves

• Experience developing and optimizing ATE test programs for wafer sort and final test on Advantest V93K platforms
• Experience managing wafer sort and final test across multiple advanced process nodes
• GPU, HPC, or AI accelerator chip testing background with production scale results
• HBM or high-speed memory interface testing and characterization experience
• Leading NPI through high-volume production with multi-vendor qualification across multiple OSAT sites
• Driving significant cost reduction initiatives
• Multi-site parallel testing strategies and test time optimization for large-format dies
• Scripting and automation skills (Python, Perl, TCL) for test data analysis and workflow automation
• Cross-functional leadership in silicon bring-up and manufacturing ramp

Responsibilities

• Planning and executing comprehensive silicon characterization from first silicon through production release, including voltage-frequency-temperature characterization, corner testing, guard band determination, and production limit setting
• Lead test cost optimization efforts while maintaining quality standards
• Architect test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs
• Drive systematic yield improvement initiatives through data-driven root cause analysis using statistical tools and methods
• Establish and track key quality metrics including DPPM and test escapes
• Perform die/package level bring-ups, troubleshoot failure modes, and resolve issues by collaborating with design, system validation, and operations teams
• Support OSAT bring-up, manage ATE/SLT manufacturing test program releases, and drive toward aggressive test cost goals
• Productize test programs and methodologies for seamless transition from engineering to high-volume manufacturing
• Analyze field return data and system-level failures to identify test coverage gaps and implement improved screening methods
• Drive ATE-system correlation activities to ensure test program accuracy and validate performance against system specs
• Manage relationships with test vendors, OSAT partners, and foundry partners

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch and dinner in our office

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Associate degree