Product Development Engineer

Altera•San Jose, CA

2d•$106,200 - $153,675•Onsite

About The Position

Altera is seeking a Product Development Engineer to join its Manufacturing Content Development Engineering Group. The group architects, develops, validates, and productizes manufacturing test content for FPGAs to screen for manufacturing defects and ensure the quality of outgoing products. The engineer will develop and implement design-for-test (DFT) strategies for FPGAs, collaborate with RTL design and verification teams, and create test plans and manufacturing test content. The role also involves pre-silicon test validation, silicon failure analysis, manufacturing test optimization, and efforts to reduce test time and product cost. The position is based in San Jose, California, and is listed for Shift 1.

Requirements

Bachelor's or master's degree in Electrical Engineering or a related field.
At least 3 years of industry experience.
Experience in IC design and IC test.
Experience with DFT methodologies such as scan chains, Memory BIST, ATPG, boundary scan, test compression, IJTAG, and JTAG networks.
Experience with test development tools such as Tessent IJTAG, Tessent MemoryBIST, FastScan, or Tessent Shell.
Experience with RTL design, synthesis, and verification flows.
Experience with fault grading, test-time analysis, test-coverage analysis, and test-yield enhancement.
Scripting skills in Python, Perl, TCL, or similar languages.
Knowledge of semiconductor manufacturing test processes.
Knowledge of digital and analog circuit fundamentals.
Eligibility for any required U.S. export authorizations.

Nice To Haves

Master's degree in Electrical Engineering or an equivalent or related engineering degree.
Experience with Tessent MBIST flows for pattern development and knowledge of memory repair schemes and memory algorithms.
Post-silicon experience, including pattern conversion, ATE pattern bring-up, and silicon characterization.

Responsibilities

Develop and implement FPGA DFT strategies, including scan insertion, BIST, and test compression.
Collaborate with RTL design and verification teams to embed testability features efficiently.
Define and implement test plans, patterns, and fault models to optimize test coverage and yield.
Develop and maintain MBIST manufacturing test content flows and scripts.
Perform pre-silicon test-pattern simulation and validation before tape-out.
Analyze test results, debug silicon failures, and provide root-cause analysis.
Work with manufacturing and test teams to optimize test time, cost, and quality.
Analyze early customer returns and drive test-hole closure activities.
Reduce test time by analyzing fallout data against test time for various IPs and optimizing overall product cost.
Stay current with industry trends and emerging DFT and test technologies.