Process Integration, Yield and Defect Reduction Engineering Manager

Intel Corporation•Rio Rancho, NM

7d•$140,830 - $231,670•Onsite

About The Position

The New Mexico Silicon Manufacturing Integration team is seeking a highly motivated engineering professional with a strong technical background to grow into a Process Integration, Yield, and Defect Reduction Engineering Manager role. In this position, you will collaborate closely with Advanced Packaging High Volume Manufacturing (HVM) technical and factory operations teams to support the transfer, ramp, and sustaining of advanced packaging solutions while ensuring delivery against foundry customer commitments. As part of the Manufacturing Integration team, you will drive process integration, yield improvement, and defect reduction initiatives that enable high-quality, high-volume manufacturing of advanced packaging technologies. You will partner across engineering organizations to identify manufacturing challenges, implement data-driven solutions, and develop scalable manufacturing processes that improve product quality, reliability, and yield.

Requirements

Master's or PhD in Electrical Engineering, Materials Science, Physics, Chemistry, Chemical Engineering, or a related technical discipline.
5+ years of relevant semiconductor manufacturing or advanced packaging experience.
Demonstrated track record of: Technology development and technology transfer.
Solving complex technical problems through innovative engineering approaches.
High levels of technical contribution throughout the product development lifecycle.
High level of technical contributions with a proven history of technology development, technical problem solving, and technology transfer through the creation of innovative solutions that demonstrate creativity and out-of-the-box thinking.
Ability to work effectively across organizational boundaries, including Process Engineering, Yield Engineering, and Product Engineering.
Excellent written and verbal communication skills.
Strong stakeholder management and interpersonal skills.
Demonstrated ability to lead and influence others without formal authority.
Ability to think and operate independently while effectively managing multiple competing priorities.

Nice To Haves

3+ years of yield analysis and defect reduction methodologies.
3+ years of Failure Mode and Effects Analysis (FMEA).
3+ years developing inline monitoring systems and manufacturing dashboards.
Deep understanding of integrated semiconductor process flows and process interactions.
Strong knowledge of defect metrology tools and capabilities.

Responsibilities

Develop and execute a comprehensive defect reduction roadmap to improve yield and product quality.
Design and implement defect scan strategies, quick-turn analyses, and parametric monitoring systems.
Leverage Win It Inline methodologies to drive continuous process improvement while meeting quality and reliability objectives.
Lead a team of process integration, yield, and defect reduction engineers in solving complex manufacturing challenges.
Collaborate with design, materials, product engineering, characterization, process development, and High Volume Manufacturing (HVM) teams to optimize manufacturing performance.
Develop scalable and cost-effective manufacturing solutions for advanced packaging technologies.
Build and maintain inline metrics dashboards for critical process modules and manufacturing parameters.