Process Integration Development Engineer - Defect Metrology

Intel Corporation•Hillsboro, OR

1d•$115,110 - $219,550•Hybrid

About The Position

At Intel's Logic Technology Development (LTD) we have continued to extend Moore's law to be world leaders in computing technology. To achieve the necessary scaling of our semiconductor manufacturing process, we have led the industry in developing enhancements such as strained silicon for carrier transport enhancement, high-k metal gates, and FINFETs. LTD has been at the center of every new development that has kept Moore's Law moving forward. Defect Metrology plays a key role in the development of every new silicon process development. Our analysis builds the plan that allows LTD to take technology from the research phase to the high-volume manufacturing phase while maintaining high quality standards. In the MIE organization, we engineer world-class yields on D1 processes by driving defects down to Best-in-Class targets. As a Defect Metrology engineer, you will be responsible for identifying all the defects that impact yield and performance in an advanced silicon process technology. You will characterize the process using cutting-edge metrology tools. With this characterization, you will be responsible for creating the defect reduction roadmap. You will then work directly with modules and integration to drive that roadmap by developing and qualifying process fixes. This role provides an opportunity to influence Intel's future process technologies that will keep Moore's Law moving forward.

Requirements

Must possess a Master's degree with 3+ years of experience, or PhD with 1+ years of experience in Computer Science, Physics, Material Science and Engineering, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Nuclear engineering, Optics, or Chemistry (with focus on hands on experimental research)
Minimum of 1 year experience with one or more of the following: Materials characterization (SEM, TEM, etc.), materials fabrication, synthesis, metrology, statistical or data analysis (MATLAB, Excel, JMP, etc.)
Semiconductor processing fundamentals (lithography, wet and or dry etch, chemical and or mechanical polishing, etc.), semiconductor and or transistor device physics, and design of experiments.
Strong data analysis and problem debug skills.
Excellent communication skills.
Understand and adhere to key Intel values

Nice To Haves

Minimum of 1 year experience with one or more of the following: Demonstrate experience of Statistical Process Control SPC or Design of Experiments (DOE) principles.
Expertise on semiconductor physics.
Expertise on semiconductor processing.
Expertise in Yield Improvement, Defect Improvement
Brightfield, Darkfield, Voltage Contrast (VC)
Experience with defect troubleshooting using programs similar or including Klarity, JMP, Model-Based Problem Solving (MBPS) or Fishbone Analysis

Responsibilities

Provide navigation and leadership to meet Intel's yield objectives utilizing state of the art metrology tools and QTMs.
Organizing and presenting defect summaries to LTD engineering teams.
Partnering with Intel Integration, Yield, and failure analysis labs to provide root cause for all defect issues.
Institute ramp to manufacturing volumes to demonstrate the technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology.
Hold the team and collaborators accountable for quality through IMT and FTs.
Work collaboratively as a part of the overall TD Defect metrology group.
Role-model and establish a team culture of trust, collaboration, safety, accountability, and excellence.
Build strong relationships with other LTD process and design teams based on mutual trust and respect.