Process Engineer 5

Lam Research•Fremont, CA

10d•$125,000 - $270,000

About The Position

The Process Engineer works in Lam Research’s Office of the CTO, supporting plasma etch process research, development, and evaluation for advanced etch equipment and systems. The role focuses on reactive ion etching (RIE), advanced patterning applications, and process formulations that enable next-generation semiconductor technologies. The position develops and optimizes etch processes for applications such as EUV and hardmask pattern transfer, multi-patterning, high-aspect-ratio features, and critical-dimension control. It analyzes process and metrology data to guide development, improve etch performance and yield, and establish process specifications. The engineer collaborates with internal teams and customers on demonstrations, technology development, product releases, and adoption of new etch and patterning technologies. The role also provides direction and guidance to process technicians. The position requires a master’s degree in a related discipline with at least eight years of experience, a PhD with at least five years of experience, or equivalent experience. Preferred qualifications include substantial plasma etch and patterning knowledge, experience with semiconductor process equipment and metrology, statistical process methods, scientific computing, and cross-functional customer collaboration. Salary for applicants residing or working onsite in the California San Francisco Bay Area is listed as $125,000–$270,000; actual offers depend on multiple factors. Lam states that it offers a comprehensive set of benefits, without specifying them in this posting.

Requirements

Master’s degree in Materials Science, Chemical Engineering, Chemistry, Physics, or a related field and at least 8 years of experience; or a PhD and at least 5 years of experience; or equivalent experience.

Nice To Haves

In-depth plasma etch background, including RIE and atomic layer etching (ALE), on inductively coupled plasma (ICP) and/or capacitively coupled plasma (CCP) systems.
Hands-on experience with EUV and 193i pattern transfer, multi-patterning (SADP/SAQP), hardmask opening, and high-aspect-ratio etching of dielectric, conductor, or metal films.
Understanding of plasma physics and plasma-surface interactions and their effects on etch rate, selectivity, profile, and CD control.
Experience with etch and patterning metrology and characterization (CD-SEM, cross-section SEM/TEM, OCD, AFM) and related failure analysis.
Familiarity with laboratory and semiconductor equipment work, including surface preparation and analytical techniques.
In-depth understanding of Statistical Process Control (SPC) and/or Design of Experiments (DOE).
High proficiency in MATLAB, Python, or a similar scientific computing language.
Experience with statistical tools such as JMP or Minitab and structured problem-solving methodologies.
Working knowledge of deposition processes (ALD, CVD, PECVD, PVD), materials characterization, and integration with etch in patterning flows.
Experience in collaborative, matrixed environments with diverse teams, semiconductor customers, and/or partners.

Responsibilities

Conduct plasma etch process research, development, and evaluation for etch equipment and systems, with emphasis on RIE and patterning applications.
Develop and optimize etch processes for advanced patterning schemes, including EUV and hardmask pattern transfer, multi-patterning (SADP/SAQP), high-aspect-ratio features, and tight CD control.
Characterize and improve etch performance, including profile, CD uniformity, selectivity, LER/LWR, loading, and defectivity, to increase yields and reduce production costs.
Compile and analyze process and metrology data, including CD-SEM, cross-section SEM/TEM, and OCD, to determine development next steps and process specification limits and variables.
Collaborate internally to plan, collect data, analyze results, and report on customer demonstrations for etch and patterning applications.
Partner with lithography, deposition, and integration teams and customers to understand patterning roadmaps, process flows, inflection points, requirements, and business challenges.
Contribute to next-generation etch product development and release activities supporting the semiconductor roadmap.
Provide leadership, direction, and guidance to process technicians in support of execution activities.
Work with customers to introduce and drive adoption of new etch and patterning technologies at customer sites.