Process Engineer 5 (Advanced Packaging Integration Technologist)

Lam Research•Tualatin, OR

20h

About The Position

The Process Engineer 5 will help expand Lam Research’s leadership in advanced packaging by leading and executing complex joint development projects (JDPs) and research programs that create business value across engineering, manufacturing, supply chain, and business operations. The role works with Lam product groups, customer account teams, ecosystem partners, and external leaders to coordinate a virtual integration center, accelerate decision-making, improve operational efficiency, and resolve challenging process integration problems. The position develops integration flows that meet manufacturability and reliability requirements and supports novel technology development. It also studies system-level co-optimization across logic and memory products, helps identify future hardware and process needs, and represents Lam as a technology ambassador at conferences and symposiums. Lam offers work-location models that may include onsite and remote work, depending on the needs of the role; the specific model for this position is not stated.

Requirements

Master’s or PhD in engineering (electrical, mechanical, or chemical), materials science, applied physics, chemistry, or a related discipline.
10 or more years of experience in semiconductor process development, packaging integration (such as TSV, WLP, HB, or panel-level packaging), model-based problem solving, program management, or related business functions in a complex enterprise environment.
Strong fundamental understanding of advanced-packaging technologies and integration, industry direction, and research initiatives.
Proficiency in statistical data analysis, process controls, and optimization, and ability to use AI tools for efficiency.
Excellent communication and problem-solving skills, with the ability to collaborate extensively within and outside Lam Research.
Demonstrated experience partnering with senior executives and business stakeholders to define strategy, prioritize investments, and deliver business outcomes.
Experience managing cross-functional programs and influencing stakeholders in a global, matrixed organization.

Nice To Haves

Experience initiating, defining, and executing joint development projects with research institutes, industry consortia, and academic institutions.
Experience in the semiconductor, capital equipment, industrial technology, or advanced manufacturing industries.
A strong network across industry ecosystems and research communities.
Ability to make high-impact decisions and keep programs on track in ambiguous situations with incomplete data.
Familiarity with laboratory work and semiconductor equipment, including surface preparation and analytical techniques.
In-depth understanding of Statistical Process Control (SPC) and/or Design of Experiments (DOE).
Working knowledge of statistical analysis and problem-solving methodologies.
Experience with statistical tools such as JMP or Minitab.
Background in Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), or Physical Vapor Deposition (PVD).
Background in plasma physics, Reactive Ion Etching (RIE), Atomic Layer Etching (ALE), Inductively Coupled Plasma (ICP), or Capacitively Coupled Plasma (CCP).
Knowledge of material synthesis and material characterization.
Experience in collaborative, matrixed environments with diverse teams, semiconductor customers, and/or partners.
Experience in semiconductor process design, deposition, or etching of dielectric or conductor materials and metal films.

Responsibilities

Provide subject matter expertise in logic and memory advanced packaging integration, including 2D/2.5D/3D, WLP, and HBM.
Translate customer advanced-packaging roadmaps into process integration flow options, identify unit-process challenges, and propose solutions to support product performance, yield, and reliability.
Work with product-group engineering and customer account technologist teams on test-vehicle needs, development, characterization, and test-vehicle flows.
Study system-level co-optimization trends across logic and memory product and process segments, identify emerging challenges, and determine critical hardware and process needs for Lam products.
Design experiments, lead data analysis, and drive systematic root-cause analysis and corrective actions to resolve process integration problems.
Work with ecosystem engagement leads and program managers to define JDP scope, objectives, KPIs or success metrics, and milestones.
Lead collaborations with peers, partners, and startups to define, execute, and implement co-optimized integration strategies and solutions.
Drive JDPs with materials suppliers and metrology companies to support co-development and characterization.
Stay current on advanced-packaging research, pathfinding, and innovations; assist product marketing leaders with market assessments, competitive intelligence, strategic initiatives, and portfolio gap analysis.
Support customer engagement meetings and escalations involving integrated problems.
Represent Lam at industry conferences and symposiums to build its network, influence, and brand.
Support mentoring and recruitment for the ecosystem team.