Principal Validation Lead

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Senior Validation Engineer (Lead) will own the lab validation strategy and execution for advanced ASIC/SoC products integrating CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes. This role combines hands-on silicon bring-up and debug with technical leadership of validation activities, including test planning, methodology, and coordination across design, DFT, firmware, and product/test engineering.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
Typically 8+ years of industry experience in silicon or system validation, including hands-on lab work.
Strong expertise in at least two of the following: CXL (2.0/3.x), PCIe (Gen4/Gen5/Gen6), DDR (DDR4/DDR5), HBM (HBM2/2E/3), high-speed SerDes.
Proven experience leading bring-up and validation of complex ASIC/SoC products from first silicon through production.
Deep hands-on experience with lab equipment (oscilloscopes, protocol analyzers, logic analyzers, BERTs, power supplies, etc.) and high-speed measurement techniques.
Strong scripting and lab automation skills (e.g., Python, TCL, shell, MATLAB) for test control and data analysis.
Demonstrated ability to drive cross-functional debug and closure, with clear communication of complex technical issues.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, or related field.
Experience leading small validation teams or acting as technical lead on multi‑site projects.
Familiarity with DFT features (scan, BIST, JTAG) and their use in bring-up and debug.
Experience with signal integrity/power integrity concepts and working with SI/PI or board design teams.

Responsibilities

Define overall validation strategy and test plans for ASIC/SoC devices with CXL 3.x, HBM, DDR, PCIe, and high-speed SerDes interfaces, covering functionality, performance, power, margining, and interoperability.
Lead silicon bring-up and lab validation, including platform bring-up (boards, power, clocks, resets) and interface‑level validation for CXL/PCIe/DDR/HBM/SerDes.
Provide technical direction to other validation engineers, including test plan reviews, debug guidance, and prioritization of tasks and issues.
Configure and operate advanced lab equipment: high‑bandwidth oscilloscopes and probes, logic analyzers, PCIe/CXL protocol analyzers, BERTs, pattern generators, power supplies, electronic loads, and environmental chambers.
Drive development of lab automation and data analysis infrastructure (Python, TCL, shell, MATLAB or similar) to improve coverage, throughput, and reproducibility.
Analyze large data sets to characterize high-speed links and memory interfaces (BER, eye diagrams, jitter, margins, throughput, latency, power) and translate findings into design and validation recommendations.
Lead root-cause investigations across silicon, firmware, board design, and test setup; coordinate cross-functional issue closure with design, DFT, firmware, and product/test engineering.
Own documentation of validation methodologies, lab setups, and results; communicate status, risks, and mitigation plans to project leadership.
Mentor and coach junior validation engineers, helping build a strong, scalable lab validation team and best practices.