Principal Validation Engineer
About The Position
As a Silicon Validation Principal Engineer at Marvell, you’ll be helping to deliver high bandwidth devices within the rack. This team performs validation on leading edge switch devices utilizing advanced Si technology nodes and advanced packaging, delivering the highest performance products in the datacenter market. Complete responsibility for PHY and functional Validation in post-silicon environment. Defining, documenting, executing and reporting the overall validation/test plan for Marvell switch devices Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack. Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. Analyze and debug issues on PHY protocol of storage interface (PCIe, UALink, Ethernet).
Requirements
- Bachelor’s degree in computer science, Electrical Engineering or related fields and 10+ years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5+ years of experience.
- Strong understanding of high-speed SERDES, equalization technique and PCIe, UALink and Ethernet protocols.
- 5+ years experience with High Speed IO testing, debugging and validation
- Strong lab skills with hands on experience, in system bring up, system testing and debug.
- In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
- Strong analytical, problem-solving and communication skills
Nice To Haves
- Working knowledge of PCIe interface and characterization.
- Working knowledge and experience on Ethernet and/or UALink is a definite plus.
- Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
- Working knowledge of board design; able to read board schematics and board layout.
- Knowledge in SERDES modeling techniques
- Working experience with Python.
Responsibilities
- Complete responsibility for PHY and functional Validation in post-silicon environment.
- Defining, documenting, executing and reporting the overall validation/test plan for Marvell switch devices
- Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
- Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
- Analyze and debug issues on PHY protocol of storage interface (PCIe, UALink, Ethernet)
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Principal
