Principal Timing Engineer

Marvell Technology • Toronto, ON

1d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. This is an existing vacancy. Your Team, Your Impact Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect ASIC design engineer responsible for post RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation and ECOs. The responsibilities include but not limited to. Improve the design methodology and flow. Synthesis, timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. Collaborate with Analog/Digital design teams to deliver the competitive SerDes IP solutions for all the Marvell product lines. Provide the support to the product teams, for both pre and post silicon.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience.
• Good personal communication skills and team working spirit.
• Hardworking and motivated to be part of a highly competent design team.
• Must have good post-RTL experience including synthesis, timing analysis and physical design.
• Able to perform custom placement and routing for mixed-signal designs.
• Flexible to move between all post-RTL design activities as required.
• Good understanding of block and top-level physical timing closure.
• Must be proficient in the following skills: Logic or physical synthesis using Synopsys or Cadence tools
• Static timing analysis using Primetime
• Physical design for 28nm and beyond
• DFT generation and verification
• Strong Perl and Tcl scripting skill

Nice To Haves

• Low power design
• IR drop analysis
• Circuit level or custom design experience
• Floorplanning, clock-tree synthesis and power planning/analysis
• Signal integrity and physical verification
• PnR flow development

Responsibilities

• Improve the design methodology and flow.
• Synthesis, timing closure and DFT support for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
• Collaborate with Analog/Digital design teams to deliver the competitive SerDes IP solutions for all the Marvell product lines.
• Provide the support to the product teams, for both pre and post silicon.

Benefits

• competitive compensation
• great benefits
• workstyle within an environment of shared collaboration, transparency, and inclusivity.
• dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal