Principal Systems Engineer, RELIC Compute Architecture

Rune•Mountain View, CA

6d•Hybrid

About The Position

The Principal Systems Engineer will own the compute architecture of next-generation RELIC, including node components, how nodes connect, and how the serving stack maps onto the hardware. Reporting to the CTO, this role sets technical direction for GPU, CPU, NIC, switch, and fabric decisions over the next two hardware generations. It is a systems-focused role spanning workload characteristics, scale-up domains, scale-out fabrics, memory hierarchy, and power envelopes, with the goal of optimizing tokens per second per megawatt and cost per million tokens. The position is based in Mountain View, California, with a hybrid schedule requiring three days per week in the office. The engineer will define and validate RELIC’s compute platforms, architecture, and roadmap; co-design inference software and hardware; build performance and total-cost-of-ownership models; and lead technical relationships with vendors. The role also includes hands-on platform bring-up and validation and resolving fabric, NIC, and node-level issues that block production.

Requirements

At least 10 years of systems architecture experience in AI, HPC, or hyperscale compute.
Experience taking at least one platform from paper to production at cluster scale.
Deep understanding of scale-up versus scale-out architectures and the ability to explain and quantify workload requirements and the costs of architectural choices.
Hands-on experience with NVLink/NVSwitch, InfiniBand, and RoCEv2, including PFC, ECN, and DCQCN; familiarity with UALink and Ultra Ethernet.
Fluency in GPU architecture, including SM and tensor-core design, HBM capacity and bandwidth, low-precision formats such as FP8 and FP4/MXFP4, and their effects on prefill versus decode.
Knowledge of Arm and x86 server architectures, including Grace, Neoverse, EPYC, and Xeon; NUMA; PCIe Gen5/Gen6; CXL; and host roles in data movement and KV-cache tiering.
Working knowledge of modern inference software and concepts, including disaggregated serving, continuous batching, paged attention, KV-cache reuse and transfer, and MoE parallelism.
Hands-on experience with at least one of SGLang, vLLM, TensorRT-LLM, or Dynamo.
Ability to build performance and TCO models from first principles and defend them with benchmarks.
Engagement with the AI/HPC ecosystem through activities such as papers, open-source projects, OCP or MLPerf work, conference talks, or deep vendor relationships.
Comfort owning ambiguous, cross-disciplinary problems at an early-stage company and working hands-on in a cluster when needed.

Nice To Haves

Background in silicon or microarchitecture, such as CPU, GPU, NPU, or network ASIC design or performance architecture.
Experience with rack-scale systems, liquid cooling, busbar or DC power distribution, and 800G/1.6T optics.
Familiarity with power electronics, DC-coupled architectures, or behind-the-meter power.
Collective-communication experience with NCCL, RCCL, NVSHMEM, or NIXL, or HPC experience with MPI-scale jobs.
Contributions to SGLang, vLLM, Dynamo, LMCache, or similar serving projects.
Experience evaluating non-GPU inference accelerators and building the business case for or against them.
Published papers or patents in computer architecture, networking, or ML systems.

Responsibilities

Define the next-generation RELIC compute platform and evaluate accelerators, host CPUs, NICs, and DPUs across NVIDIA, AMD, and emerging inference silicon.
Select between HGX-class nodes and rack-scale NVL systems for each site.
Architect scale-up domains, including NVLink/NVSwitch sizing and partitioning, while tracking alternatives such as UALink and Ethernet-based scale-up.
Architect scale-out and front-end fabrics, including topology, RoCEv2 congestion control, Ultra Ethernet readiness, optics and transceiver strategy, and storage and KV-cache networks.
Co-design the inference stack with hardware by mapping disaggregated prefill/decode, KV-cache transfer and offload, MoE expert parallelism, tensor and pipeline parallelism, and speculative decoding onto the platform.
Work hands-on with SGLang, vLLM, TensorRT-LLM, and NVIDIA Dynamo.
Build and own performance, roofline, and TCO models covering throughput, latency SLOs, performance per watt, cost per token, and tokens per second per megawatt; validate models against cluster measurements.
Own the hardware roadmap and technical relationships with NVIDIA, AMD, OEMs, and network vendors; lead technical deep-dives and influence early-access programs.
Write architecture specifications for procurement and site teams.
Lead bring-up and validation of new platforms and drive root-cause analysis of fabric, NIC, and node-level production issues.