Principal System Engineer

Renesas Electronics•San Jose, CA

4d•$220,000 - $250,000•Onsite

About The Position

As a Principal System Engineer/Product Definer in our Power Management Group, you will be the primary architect defining the next generation of processor core (VCORE) power solutions for laptops and Edge AI platforms. You will own the product definition for multiphase voltage regulator (VR) solutions that power leading x86 CPU/APU and Edge AI SoCs, ensuring full compliance with Intel IMVP (IMVP9 / IMVP9.1 and successor) and AMD SVI2 / SVI3 serial-VID specifications. This high-impact role connects the compute-silicon vendors who define the core-power specifications (Intel, AMD, and NVIDIA) with the OEMs who build the end platforms (e.g., Dell, HP, Lenovo), aligning both with internal R&D to ensure Renesas delivers best-in-class solutions for efficiency, load-transient response, and power density in the thermally- and space-constrained laptop and Edge AI form factors.

Requirements

BS/MS in Electrical Engineering (Power Electronics emphasis preferred); PhD is a plus.
Minimum 12 years of semiconductor experience, with a focus on multiphase DC-DC converters and processor core-rail (VCORE) regulation for laptop and/or Edge AI platforms.
Hands-on product-definition experience with Intel IMVP-compliant and/or AMD SVI2/SVI3 VR solutions is strongly preferred.
Proficiency in system design and simulation tools such as SIMPLIS/SIMetrix, MATLAB, or Cadence-based environments for multiphase VR modeling.
Deep knowledge of Power Delivery Networks (PDN), PCB parasitics, multiphase control (AVP/load-line, current balancing, phase shedding), and serial-VID interfaces (Intel SVID, AMD SVI2/SVI3, PMBus).
Proficiency in Python or C for behavioral modeling and task automation.
Proven track record of interfacing with OEM’s or Intel/Amd technical leadership.

Nice To Haves

Familiarity with NVIDIA OpenVReg (OVR) specifications (e.g., OVR4-22, OVR16) and PWMVID-based multiphase core power for GPU / Edge AI platforms is a strong differentiator.

Responsibilities

Customer Architecture Definition: Collaborate directly with laptop OEMs/ODMs and compute-silicon vendors (Intel, AMD, and Edge AI/GPU silicon partners) to translate platform power requirements, IMVP/SVI compliance targets, RFI into Engineering Requirements Specifications with architectural and electrical specifications for the VCORE, VCCSA/SoC and GT/NPU rails.
System Architecture & Efficiency Analysis: Conduct topology identification, phase-count optimization, and detailed efficiency studies for multiphase buck / SPS (Smart Power Stage / DrMOS) core-rail architectures using system-level simulation tools (e.g., SIMPLIS, MATLAB, or similar). Develop high-fidelity behavioral models to evaluate architectural trade-offs, Adaptive Voltage Positioning (AVP) load-line, DVID/dynamic-VID transients, and loop stability against Intel IMVP and AMD SVI transient and light-load (phase-shedding) requirements.
Schematic & Layout Analysis: Review and update system models based on PCB schematics and layouts to account for real-world PDN parasitics (ESL/ESR) and the “last-inch” interconnect that constrains transient performance in dense laptop and Edge AI boards.
Technical Leadership: Lead cross-functional teams (Design, Marketing, Applications) during architecture reviews, silicon-vendor compliance reviews, and platform bring-up. Collaborate closely with IC Design teams to identify the optimal controller + power-stage partitioning and the SVID/PMBus digital feature set required to meet complex IMVP/SVI system specifications.
Strategic Roadmapping: Identify long-term value-creation avenues in Edge AI/NPU core power, high-current vertical power delivery, and next-generation IMVP/SVI feature adoption to keep the roadmap ahead of rising SoC currents and tightening efficiency targets.
Problem Solving: Act as the final technical escalation point for customers, using structured methods, system knowledge and experience to resolve complex system issues.