About The Position

The DCE team at Marvell is seeking a Principal Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes. Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites. If you're looking to apply your STA expertise in a dynamic and forward-thinking environment, this could be a great opportunity to explore.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree
  • Proven success in timing analysis and closure across multiple ASICs/SoCs
  • Experience with advanced timing concepts: SI, CDC, LVF, POCV, etc.
  • Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX environments
  • Strong communication skills and ability to work independently and collaboratively

Nice To Haves

  • Experience leading timing closure efforts across teams preferred
  • Familiarity with timing methodology and flow development preferred

Responsibilities

  • Lead timing closure for sub-system/partition or full-chip level designs
  • Collaborate with RTL, DFT, and IP teams to drive iterative timing feedback and closure
  • Deliver timing collateral and signoff reports per project milestones
  • Perform timing correlation between PD tools and signoff tools; support early feasibility studies
  • Generate and push down ECOs to block-level teams
  • Mentor junior engineers and provide technical leadership across teams
  • Develop automation scripts in Perl, Python, and TCL to improve timing workflows
  • Manage timing constraints compatible with synthesis, P&R, and STA tools

Benefits

  • employee stock purchase plan with a 2-year look back
  • family support programs
  • robust mental health resources
  • recognition and service awards
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service