Principal SoC Architect, Robotics and Automotive

NVIDIA•Us, CA

About The Position

NVIDIA is seeking a Principal SoC Architect to join our architecture team and drive the next generation of Edge AI, Robotics, and Autonomous Driving platforms. NVIDIA is developing processor and system architectures that power the world’s most advanced autonomous machines—from factory-floor AMRs and humanoids running NVIDIA Isaac, to next-generation software-defined vehicles running NVIDIA DRIVE. In this position, you will own the architectural definition of SoCs that bring together NVIDIA GPUs, world-class computer vision accelerators, and real-time processors into a single silicon fabric. Your role will be inherently cross-disciplinary, bridging the gap between pioneering robotic applications, automotive safety standards, and silicon design.

Requirements

15+ years of deep architecture design experience in high-performance silicon.
Meaningful industry expertise in top-level SoC definition
Practical knowledge of high-speed interfaces (PCIe, GMSL/Camera interfaces, Time-Sensitive Networking/TSN).
Experience with Advanced Subsystems: Multimedia/vision accelerator pipelines, CPU/GPU cache coherency, Virtualization, and Hardware Security.
Deep understanding of hardware support for real-time operating systems (RTOS), deterministic latency, and mixed-criticality workloads.
Exceptional ability to communicate, negotiate, and solve technical hurdles across all abstraction levels—from micro-architecture to software application layers.
Master’s or PhD degree in Computer Engineering, Electrical Engineering, or equivalent experience.

Nice To Haves

Experience in functional safety and building end to end solutions fulfilling safety requirements
A proven background in mapping complex Edge AI workloads ( e.g., transformer-based vision models, SLAM, or path planning) directly onto custom hardware architectures.
Advanced programming skills in SystemC, C++, or Python for architectural simulation and modeling.

Responsibilities

Define and drive the hardware architecture from early concept through bring-up and ecosystem enablement.
Collaborate with software, deep learning, and safety teams to co-design hardware feature sets tailored for low-latency robotics spatial computing, sensor fusion, and autonomous driving pipelines.
Perform rigorous performance, power, and area modeling, optimizing specifically for thermally constrained robotic enclosures and automotive ECUs.
Author high-quality architecture specifications and drive the development of models to validate architectural choices.
Define validation plans to ensure hardware meets strict real-time execution and safety metrics.
Participate in silicon debug, performance tuning, and the generation of user documentation for tier-1 robotics and automotive customers.