Principal Silicon Technology Engineer

Advanced Micro Devices, IncSan Jose, CA
Hybrid

About The Position

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. We are seeking an exceptional Principal Engineer to serve as a technical authority and strategic contributor across the full product lifecycle of FPGA and ASIC solutions. This role encompasses advanced silicon technology evaluation, design enablement, process development, and manufacturing bring-up — spanning from early concept exploration through qualification and transfer to high-volume production (HVM).

Requirements

  • Familiar with advanced silicon technologies including manufacturing process, device physics, reliability mechanisms as well as foundry PDK support.
  • A good understanding of FPGA and ASIC product development and yield ramp-up is desired.
  • The candidate shall possess effective communication, good interpersonal skills and be able to work seamlessly with design teams, foundry partners and package/assembly vendors.
  • Familiar with advanced semiconductor technologies including FinFET, GAA, Backside Power etc.
  • Past experience of supporting product silicon development and NPI is required
  • Strong background in development and tape out of process and IP validation test vehicles
  • Working knowledge of IP and SoC analog and digital design flows with foundry PDK support experience
  • Experience with major EDA tools for device model, layout, circuit simulation, parasitic extraction, and physical verification
  • Familiarity with device reliability degradation mechanisms, test methods, and lifetime modeling
  • Strong analytical, problem solving, decision-making and communication skills

Nice To Haves

  • Working knowledge of 3DIC advanced packaging technologies including CoWoS and SoIC is a plus
  • Prior team leadership and management experience is a plus

Responsibilities

  • Responsible for technology evaluation, design enablement and process development of FPGA and ASIC products in advanced nodes
  • Responsible for product WAT analysis, performance correlation and yield analysis during NPI in collaboration with foundry and design teams
  • Coordinate testchip design and tapeout for process and IP validation prior to NPI phase
  • Co-work with design, CAD & PDK teams to accomplish robust IP & product designs
  • Assist Silicon technology roadmap exploration to meet end customer requirements

Benefits

  • AMD benefits at a glance.
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