Principal Silicon Product Engineer

Google•Sunnyvale, CA

5h•$281,000 - $391,000

About The Position

As the Principal Silicon Product Engineer, you will serve as the chief technical authority for the Silicon Sourcing organization bridging hardware engineering design, global manufacturing ecosystems, and strategic sourcing across the entire silicon lifecycle. While our commercial leads focus on master service agreements, capacity reservations, and multi-billion-dollar contract structures, you will lead the technical arm of the organization. You will drive deep architectural, manufacturing, and product engineering evaluations across both Custom Silicon (ASICs/COT: TPUs, gSOC, custom networking/accelerators) and Off-the-Shelf (OTS: GPUs, x86 CPUs, Memory, Storage, Strategic Silicon). You will be deeply embedded across all phases of the silicon product lifecycle—from early silicon architecture and process node selection to NPI, DFM/DFT validation, wafer fab yield modeling, advanced packaging integration, and test engineering optimization. You will be the authoritative technical partner to internal Platforms Engineering, Systems Architecture, and Cloud Supply Chain Operations teams, translating complex semiconductor physics and manufacturing realities into actionable sourcing leverage, risk mitigation, and performance breakthroughs. You will engage directly with CTOs, VP-level engineering leaders, and fellow-level technical teams at Tier-1 foundries (TSMC, Intel), major merchant silicon vendors (AMD, Broadcom, Marvell), advanced OSATs, and sub-tier material suppliers. You will establish rigorous technical "should-cost" foundations, evaluate cutting-edge process nodes (sub-2nm), de-risk advanced heterogeneous packaging (CoWoS, 3D, HBM), and define yield/test parameters that optimize Total Cost of Ownership (TCO). Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $281000 - $391000 (USD) + 30% bonus target + equity + benefits Learn more about benefits at Google [https://www.google.com/about/careers/applications/benefits/].

Requirements

15 years of relevant experience in Semiconductor Product Engineering, Silicon Architecture, Foundry Engineering, or Technical Sourcing Engineering.
Experience with semiconductor product lifecycle: design tape-out, wafer fab processing, parametric yield analysis, advanced packaging/assembly, and high-volume test engineering (ATE/SLT).
Experience evaluating and scaling leading-edge nodes (3nm, 2nm, and beyond) and heterogeneous packaging technologies (2.5D/3D, CoWoS, chiplets, HBM).
Experience covering both Custom ASIC/COT flows and standardized high-performance compute silicon (GPUs, x86/ARM CPUs, high-speed networking, and memory architectures).

Nice To Haves

Master’s degree or Ph.D. in Electrical Engineering, Microelectronics, Materials Science, or related technical field.
Experience with silicon execution vehicles (eTV/mTV), silicon photonics integration, advanced cooling/thermal interfaces, and custom AI accelerator hardware bottlenecks.

Responsibilities

Serve as the principal technical authority across Custom Silicon (TPUs, gSOCs, ASICs) and OTS products (Switches, PCIe, CXL, CPUs), evaluating vendor technical capabilities, architectural trade-offs, node roadmaps, and manufacturability.
Work with engineering to help conduct rigorous technical evaluations of leading-edge process nodes (sub-2nm, GAA/RibbonFET, backside power delivery) and specialized nodes. Partner with Tier-1 foundries to assess defect densities, DFM/PDK compliance, and process window margins to secure optimal node execution.
Architect and qualify heterogeneous integration paths (CoWoS, InFO, 3D stacking, HBM integration) and sub-tier components (substrates, thermal interface materials), establishing stringent mechanical and thermal readiness gates (e.g., mTV/eTV stress testing).