Principal Silicon Engineer

Microsoft • In, IN

20h

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives. We’re seeking a Static Timing Analysis experienced individual. As part of our DPU silicon team, you’ll take on the challenge of driving our STA execution from early design exploration to signoff. You’ll work across teams to define, develop, and drive all aspects of the design flow to make our STA signoff successful. We’re working on some of the most exciting silicon projects in Microsoft, and you will help us drive our vision.

Requirements

• Bachelor’s degree in computer engineering, electrical engineering, or related field
• 7+ years of physical design/STA experience
• Experience with Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime)

Nice To Haves

• 10+ years of hands-on physical design experience with focus on STA execution and signoff
• Deep expertise in STA, timing constraints, ECO generation, and STA signoff procedures
• Proficiency in flow automation, scripting (TCL/Perl) & tool debug
• Ability to develop & maintain timing closure checklists, to track and report STA progress through all design phases, and successfully execute STA closure on schedule
• Demonstrated tapeout experience in TSMC 5nm process or below

Responsibilities

• Take ownership and responsibility for our STA execution
• Develop, improve, and update our STA methodology; work closely with vendors to align our flows to industry practices, resolve tool issues, and improve overall execution and reliability of STA flows
• Take an active role in early-phase design planning with STA execution including full-chip repeater planning, timing budgeting, constraint development, and early analysis
• Define & drive to STA milestones across project phases; manage STA rollups, analysis & reporting, ECO generation flows, and guidance to block development
• Ensure a convergent STA process and drive STA closure through all phases including final signoff for tapeout
• Work across teams to identify and resolve boundary timing issues, fullchip STA bottlenecks, etc.
• Give guidance for floorplan adjustments and address timing issues, constraints, etc.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal