Principal Silicon Design Verification Engineer

Microsoft•Redmond, WA

18h•$142,800 - $304,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering core infrastructure and foundational technologies for over 200 Microsoft online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft's state-of-the-art computer chips, including the Azure Cobalt. The Silicon IP and Custom Products (SCIPS) team within CSME is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving planning processes, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. This role is for a Principal Silicon Design Verification Engineer within the SCIPS team, focused on envisioning and implementing future technical solutions to manage and optimize cloud infrastructure.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must be able to access information controlled for export under export control regulations (e.g., ITAR, EAR, EU Dual Use Regulation).
Must provide proof of country of citizenship or US residency/protected status for assessment of eligibility to access export-controlled information.
Citizenship will be verified with a valid passport; lawful permanent residents, refugees, and asylees may verify status using other documents.

Nice To Haves

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
Experience developing tests in C/C++, SystemVerilog, and UVM, with emphasis on C/C++ test content for subsystem and SoC verification.
Experience leading pre-silicon verification of IP, subsystems, and SoCs through the full cycle, including SoC-level testbench development, test planning, and coverage signoff.
In-depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs.
Experience directing and mentoring individual engineers.
Experience collaborating across architecture, design, block-level DV, and firmware teams to execute functional verification, with communication skills.
Understanding of silicon and/or computer architecture.
Proficiency in a scripting language such as Python, Ruby, or Perl.
Experience with emulation, FPGA prototyping (such as HAPS or Xilinx), RTL design for FPGA or emulation, or post-silicon validation.
Experience with assembly, startup code, linker scripts, and Makefile-based build flows for software development.
Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, or USB.
Hands-on hardware debug experience with tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.

Responsibilities

Own the development of C and C++ based test content at the subsystem and SoC levels, including bare-metal bring-up code, directed and constrained-random test sequences, and self-checking tests that exercise complex multi-IP flows such as secure boot, key and fuse management, and processor and bus interactions.
Build and maintain the C test infrastructure that the broader team relies on, including startup code, low-level drivers, register access layers, and the build flow (Makefiles, linker scripts, and toolchain setup) needed to compile and run firmware-style tests against the design.
Own the pre-silicon verification strategy and execution for one or more security IP blocks and subsystems and their integration into the SoC, covering test planning, environment architecture, and signoff criteria from early design through tapeout and silicon bring-up.
Architect and extend SystemVerilog and UVM environments that host C-based stimulus, connecting embedded test code to the testbench so processor-driven and stimulus-driven scenarios run together.
Drive coverage signoff across functional, code, and power-aware coverage. Set goals, investigate and close gaps without unjustified exclusions, and apply constrained-random, formal, and gate-level techniques to find bugs and prove test plan completeness.
Act as verification lead and technical point of contact for customer and partner teams, owning milestone delivery at both the IP and SoC levels, keeping releases on schedule.
Mentor and guide less experienced engineers by reviewing test plans, C and SystemVerilog code, debug work, onboarding new team members, and establishing verification best practices the broader team can reuse.
Improve verification efficiency by building reference and prediction models, automation, and debug tooling in Python and other scripting languages, and by correlating pre-silicon C test results with FPGA prototyping platforms to accelerate firmware bring-up and post-silicon validation.