Principal SerDes Validation Engineer

Marvell Technology•Santa Clara, CA

1d•$150,680 - $225,700

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC’s, used in many communication infrastructure applications such as 5G base stations, NICs, Data Center and Cloud Computing platforms. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SERDES interfaces for various applications on the products. Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production.

Requirements

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
Strong understanding of high-speed SERDES, equalization technique and PCIe/Ethernet protocols.
5+ years experience with High Speed IO testing, debugging and validation
5+ years of direct experience in SERDES characterization/design.
In depth knowledge of SERDES interface using NRZ and PAM4 signaling for Ethernet and PCIe interfaces, knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE) is a plus.
In depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer etc.).
Deep understanding of high-speed electrical signaling principles, differential signaling and mixed-signal designs.
Experience in Python programming language for automation framework development, as well as mathematical programing such as Matlab.
Critical thinking and problem-solving attitude and ownership of the group’s results.
Knowledge in SERDES modeling techniques
Excellent verbal and written communication skills.

Nice To Haves

knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE) is a plus.

Responsibilities

Complete responsibility for PCIe/Ethernet PHY Validation in post-silicon environment.
Defining, documenting, executing and reporting the overall PHY validation/test plan for Marvell storage devices
Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
Analyze and debug issues on Phy protocol of storage interface ( SATA, SAS, PCIe, Ethernet )
Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
Leading collaborative technical discussions to drive resolution on technical issues
Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY.
Work closely with customers to address design issue and debug failure cases