Principal RTL Methodology Architect

Ericsson•Austin, TX

21h•Onsite

About The Position

We are Ericsson Silicon — and we're building the future of 5G from the transistor up. Our Silicon Engineering unit is at the bleeding edge of ASIC and FPGA development, targeting the most advanced technology nodes on the planet to power Ericsson's next-generation 5G telecommunications portfolio. This isn't just a job — it's a chance to leave your fingerprints on silicon that connects the world. With a team packed with world-class engineers and virtually unlimited opportunities to grow, this is where elite talent comes to do the best work of their careers. We're looking for a Principal RTL Methodology Architect — a rare breed of engineer who can think at the system level, execute at the RTL level, and lead at the organizational level. You'll be the driving force behind scalable frontend design methodologies deployed across global engineering teams, raising the bar on RTL quality, reuse, and development velocity. You won't just write the rules — you'll build the infrastructure that enforces them. This role demands someone who thrives at the intersection of methodology leadership and hands-on silicon execution — someone equally comfortable defining enterprise-wide lint signoff frameworks as they are deep in microarchitecture development on critical silicon blocks. And if that weren't enough? You'll be on the frontier of AI-driven silicon design, pioneering how machine intelligence transforms the way we build chips: AI-accelerated RTL code generation and design productivity, Intelligent linting and next-gen static analysis, AI-optimized design space exploration and microarchitecture decisions, Automated frontend design and verification workflows powered by ML. This is your opportunity to help redefine what silicon development looks like in the age of artificial intelligence.

Requirements

RTL Mastery — Deep, battle-tested expertise in SystemVerilog/Verilog design, microarchitecture definition, and implementation for complex ASIC and SoC designs
Architecture at Scale — Proven leadership defining and deploying enterprise-scale RTL methodologies and frontend CAD architectures across global organizations
Lint-First Champion — Expert command of SpyGlass and Synopsys VC SpyGlass/VC Lint for rigorous RTL quality signoff
Structural Validation Expert — Extensive knowledge of CDC analysis, static quality gates, and pre-silicon design signoff frameworks
IP Reuse Architect — Deep background building reusable RTL frameworks, standardized interfaces, and multi-program reuse strategies that actually scale
Low-Power Guru — Hands-on experience with UPF-aware design, power domains, isolation, and retention strategies
EDA Power User — Proficient across VCS, Xcelium, Questa, linting, CDC, and synthesis integration flows
Automation Builder — Strong Python and scripting skills with real experience deploying CI/CD pipelines and design quality dashboards
AI Visionary — Genuine passion for applying AI/ML to transform RTL productivity, intelligent static analysis, and next-generation frontend automation

Responsibilities

Architect and deploy RTL design methodologies and frontend flows across IP, subsystem, and full SoC programs
Define and enforce RTL quality signoff frameworks — lint, CDC, static analysis — baked directly into CI-driven development pipelines
Champion lint-first design culture and establish standardized RTL coding guidelines and quality metrics that teams actually adopt
Build and scale reusable IP platforms and configurable RTL frameworks powering efficient multi-program silicon development
Optimize frontend design flows integrating static analysis, simulation, and synthesis readiness at every stage
Stay hands-on — approximately 50% of your time contributing directly to microarchitecture development and critical silicon block implementation
Deploy automation frameworks and CI/CD pipelines that measurably accelerate design productivity, regression efficiency, and quality tracking

Benefits

Choice of three medical plan options
Dental plan option
Company credits towards medical and dental premiums
The Ericsson US 401(k) Plan offers an automatic 3% company contribution
Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
Company credits for basic life insurance and basic accidental death and dismemberment coverage
Company credits for short-term and long-term disability coverage
Option to participate in Ericsson’s Stock Purchase Plan
15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave at 100% of pay
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs