Principal Product Engineer - Virtual Protocols

Cadence Design Systems•San Jose, CA

1d•Onsite

About The Position

This Principal Product Engineer position is with the Virtual Protocols Product Engineering Team, responsible for the successful field readiness and customer deployment of our Transaction Based Acceleration and Virtual Emulation-based System Verification products. This position presents exciting opportunities and challenges of becoming an expert in System Level Software Driven Verification use models that leverage advanced protocol engines operating on Cadence’s Palladium and Protium Emulation products to enable the critical shift-left of System Level SOC verification and Validation for Cadence customers. This position provides opportunities to expand your software, hardware, and advanced protocol knowledge while engaging with the world’s most advanced SOC customers. The Virtual Protocol Principal Product Engineer has the opportunity to be an expert in many different areas based on their interests and career goals. Their responsibilities can be but are not limited to: Using expertise in OS, kernel, and driver SW development to support Cadence VirtualBridge products that combine a Virtual Machine running a production OS with the customer’s SOC Design running on Cadence’s Palladium emulation or Protium Prototyping platforms. Using Verification methodologies and SW development expertise to help customers utilize Cadence’s Accelerated Verification IPs and advanced APIs and verification Methodologies to accelerate and shift-left their pre-silicon SOC verification and System validation Coverage. Using protocol expertise to drive the requirements and deployment of new protocol products and features in crucial industry standard protocols like PCIe, CXL, Ethernet, USB, AMBA. Using emulation and prototyping expertise to drive virtual product performance and supporting customers in getting the most out of their Hardware platform investment and meet their validation goals.

Requirements

Protocol knowledge - PCIE, CXL, Ethernet, USB, AMBA (any preferred)
Verification Methodologies (UVM SystemVerilog / Virtual Prototyping SystemC / Portable Stimulus)
Software development (C/C++ /Object Oriented programming / Linux Kernel/Driver Development)
SOC design and verification experience (preferred)
Hardware emulation experience (preferred)
HDL language knowledge (SystemVerilog, VHDL)
Scripting language knowledge (shell, python, perl)
Compiler tools (make, gcc/g++)

Responsibilities

Developing, Maintaining, and delivering feature-based training for new products/features
Delivering critical knowledge and guidance to customers and field teams enabling customer success using Cadence emulation platforms and products.
Deploying new and emerging protocol products to bleeding-edge innovative customers working on advanced SOC and System designs
Using expertise in OS, kernel, and driver SW development to support Cadence VirtualBridge products that combine a Virtual Machine running a production OS with the customer’s SOC Design running on Cadence’s Palladium emulation or Protium Prototyping platforms.
Using Verification methodologies and SW development expertise to help customers utilize Cadence’s Accelerated Verification IPs and advanced APIs and verification Methodologies to accelerate and shift-left their pre-silicon SOC verification and System validation Coverage.
Using protocol expertise to drive the requirements and deployment of new protocol products and features in crucial industry standard protocols like PCIe, CXL, Ethernet, USB, AMBA.
Using emulation and prototyping expertise to drive virtual product performance and supporting customers in getting the most out of their Hardware platform investment and meet their validation goals.