We are seeking a Principal Full-Chip Physical Verification Engineer to lead our full chip Physical Verification efforts. This role involves owning execution plans, schedules, and driving accountability for quality, milestones, and tapeout readiness. The engineer will conduct full chip and block PV checks, ensuring ownership of full chip verification and collaborating with internal analog teams for clean IP delivery. Responsibilities include running and analyzing DRC/ERC/LUP/PERC results, and working with advanced TSMC DRC rules. This role also requires cross-functional collaboration with analog, block, and chip top owners to ensure a clean floorplan, provide early guidance on corner case requirements, influence floorplan constraints, hierarchy, and implementation strategy, and participate in tapeout readiness reviews.
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Job Type
Full-time
Career Level
Principal