Principal Package Design Engineer

Renesas Electronics•Austin, TX

14h•Hybrid

About The Position

We are seeking a Principal Package Design Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architecture, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, applications, product engineering, manufacturing, suppliers, and quality teams. The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production.

Requirements

MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field.
5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration.
Strong hands-on knowledge of advanced packaging technologies, materials, assembly processes, and application system integration as they apply to AI infrastructure and data center power management.
Deep understanding of thermal, mechanical, and electrical interactions in package design and extensive, hands-on model setup, simulations, and analysis.
Strong background in CAD and simulation tools.
Experience with package reliability testing and qualification standards.
Experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains.
Proven ability to troubleshoot packaging failures, drive root cause/corrective action, and demonstrate strong project leadership and cross-functional communication skills.

Nice To Haves

Master’s or PhD in a relevant engineering discipline.
Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules, and their applications in consumer, industrial, automotive, and high-performance computing markets.
Experience with power products in high-performance computing, AI/ML hardware, or mobile products.
Hands-on experience with tools for package design and simulation such as: Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, JMP / Minitab.
Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods.
Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging.

Responsibilities

Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding, Wafer-level packaging (WLP/FOWLP), Panel-level packaging (laminate, molding), 2.5D/3D packaging, System-in-package (SiP), Ball grid array (BGA/CSP), Wafer-to-wafer and die-to-wafer heterogeneous bonding.
Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements with hands-on, deep simulation expertise.
Drive package technology and OSAT selection and development for new product introductions (NPI).
Work closely with IC design, product definers, substrate, board, thermal, reliability, applications, and manufacturing teams to ensure package compatibility and performance.
Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy.
Perform and guide others on simulations and analysis related to signal integrity / power integrity, thermal performance, mechanical stress / warpage, and design for manufacturability (DFM).
Develop assembly flows and process requirements for OSATs and manufacturing partners. Lead package qualification activities, including DOE planning, failure analysis, and reliability testing.
Resolve packaging-related issues and challenges during NPI prototype builds, qualification, and production ramp. Collaborate with suppliers and internal/external manufacturing partners on process improvements, material evaluation, and yield optimization.
Create and maintain package specifications, design rules, process documentation, and technical reports. Mentor junior engineers and provide technical leadership across packaging initiatives.