Principal Modem SoC Engineer - Terawave
About The Position
Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. The Principal Modem SoC Design Engineer serves as a technical authority for the design of advanced ASICs enabling next-generation Satellite communication systems. This role is responsible for crafting architecture, guiding implementation strategy, and driving critical technical decisions across one or more silicon programs.
Requirements
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
- 12+ years of ASIC design experience, including ownership of complex chips or multiple tape-outs.
- Expert-level knowledge of digital design, microarchitecture, and full-chip tradeoffs.
- Proven success leading technically exciting silicon programs.
- Strong understanding of communication signal-processing hardware and system integration.
- Ability to influence across organizations and communicate complex technical topics clearly.
Nice To Haves
- Deep expertise in Space based communications, digital modems, phased arrays, or payload processing.
- Experience in advanced FEC architectures, timing recovery, carrier recovery, or channel adaptation hardware.
- Familiarity with rad-hard, fault-tolerant, or high-availability digital design techniques.
- Experience guiding architecture across both commercial and mission-critical applications.
- Strong record of innovation, patents, publications, or major product launches.
Responsibilities
- Define top-level or cross-subsystem digital architecture for Satellite communication ASICs and SoCs.
- Lead hardware realization of key communication functions such as modem pipelines, coding engines, digital beamforming, switching fabrics, and packet/data processing.
- Drive end-to-end technical planning from concept through silicon validation.
- Establish system-level tradeoffs among throughput, latency, power, die area, reliability, and manufacturability.
- Provide technical leadership across design, verification, physical design, firmware, packaging, and system teams.
- Review and influence architectural partitioning between ASIC, FPGA, software, and RF/analog domains.
- Develop methodologies and reusable IP strategies that improve schedule, quality, and scalability.
- Mentor technical leaders and act as a go-to expert for critical design reviews and issue resolution.
- Support roadmap planning and future product definition.
Benefits
- Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
