Principal Mixed Signal Architect

Blue Origin • Southgate, WA

14h • Hybrid

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! We are seeking a Principal Mixed-Signal Architect to lead the definition and development of high-performance mixed-signal subsystems for advanced communication and data-conversion SoCs. This role will own architecture, top-level specifications, behavioral modeling, IP strategy, and cross-functional integration for critical mixed-signal building blocks such as SerDes, ADCs, PLLs, VGAs, TIAs, and quantizers. The ideal candidate brings deep expertise in high-speed mixed-signal IC design, strong system-level insight, and a proven track record delivering complex products in advanced process nodes.

Requirements

• Bachelor of Sciences Degree in Electrical Engineering with a focus on Analog/Mixed-Signal design.
• 15+ years of experience in mixed-signal IC design.
• Proven track record delivering high-speed SerDes (16G/32G/56G/112G) and high-speed ADCs such as SAR, Pipeline, or Sigma-Delta architectures.
• Deep experience in advanced FinFET process nodes (7nm, 5nm, or below).
• Strong expertise managing layout-dependent effects (LDE), electromigration, and other advanced-node implementation challenges.
• Expert knowledge of industry-standard design and simulation tools including Cadence Virtuoso, Spectre /HSPICE, and AMS Designer.
• Strong understanding of mixed-signal system architecture, performance tradeoffs, and silicon validation.
• Experience working across architecture, circuit design, RTL, packaging, and lab validation teams.

Nice To Haves

• MS or PhD in Electrical Engineering with a focus on Analog/Mixed-Signal design.
• Familiarity with EM simulation tools such as EMX or Ansys.
• Understanding of high-speed interface and networking protocols such as PCIe Gen5/Gen6 and Ethernet.
• Experience defining calibration, adaptation, and equalization schemes for high-speed links and data converters.
• Background in system modeling and architecture evaluation for communication or sensor-interface applications.
• Experience partnering with packaging teams on signal integrity, substrate noise, and high-speed integration challenges.
• Strong lab bring-up and post-silicon debug experience for mixed-signal silicon.

Responsibilities

• Own top-level specifications for mixed-signal subsystems, including: Link budgets for SerDes (PAM4/NRZ) ENOB/SNDR targets for high-speed ADCs
• Develop high-level behavioral models in MATLAB, Simulink, or SystemVerilog -AMS to validate system performance before circuit implementation
• Evaluate make-versus-buy decisions for SerDes and ADC IP and recommend the best technical and business path. For internally developed solutions, lead circuit architecture and design implementation of key analog/mixed-signal blocks such as PLLs, VGAs, TIAs, and quantizers
• Define calibration and adaptation algorithms, including FFE, DFE, and adaptive gain control, that are implemented in RTL and used to optimize analog block performance
• Partner with packaging and physical design teams to define pinouts, bump maps, guard rings, and isolation strategies that minimize noise coupling between high-speed analog and noisy digital logic
• Drive cross-functional architecture tradeoffs across analog, digital, packaging, and system teams
• Lead post-silicon validation of mixed-signal subsystems in the lab using high-speed test equipment such as oscilloscopes and BERTs.
• Support debug, characterization, and performance correlation between simulation and silicon results.
• Provide technical leadership and mentorship across mixed-signal architecture and design activities.

Benefits

• Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
• Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal