Principal High-Speed Analog Mixed Signal Design Engineer

Marvell Technology•Santa Clara, CA

1d•$174,530 - $261,400

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Marvell's Central Engineering organization provides the most advanced and key analog IPs to all businesses within Marvell: including Data Center, Networking, Automotive, Storage, Security. You’ll be part of a key analog team that makes an outsized impact not only for the organization but also to the technological arc of innovation for future generations of Marvell's high-speed wireline and optical products.

Requirements

MS/PhD in Electrical Engineering and 10+ years of demonstrated experience in high-speed and low-power design on advanced CMOS technologies in the following areas: Analog Front Ends (TX Driver, TIA, CTLE, VGA), Data Converters, Voltage Regulators, Clock Generation and Distribution, DLLs, custom high-speed digital circuits.
Proven track record of successfully bringing multiple tape-outs to production.
Ability to independently assess design trade-offs and select the best one based on business needs and implementation risk.
Ability to identify, analyze, and resolve complex design challenges and issues, ensuring robust and reliable circuit performance.
Ability to technically coordinate the work of junior employees, providing mentorship and guidance.
Experience in overseeing layout engineers, providing guidance on best practices, and ensuring that layout designs meet performance, area, and reliability requirements.
Proficiency in post-silicon validation, including hands-on experience with lab equipment, debugging, and characterization of analog mixed-signal circuits.
In-depth knowledge of CMOS process technology, device physics, and the impact of process variations on circuit performance.
Proficient in using electronic design automation (EDA) tools for schematic capture, simulation, layout, and verification, such as Cadence, Synopsys, or Mentor Graphics.
Very good understanding of related areas such as RTL, Firmware, Design Verification, Design for Test, and Physical Design.
Strong communication and teamwork skills.

Nice To Haves

Extensive experience in high speed TIA and/or TX Driver design is a plus

Responsibilities

Ownership of complex design blocks and complete analog macros.
Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication, and high-speed wireline design in general.
Lead and contribute to the design of TIA, TX Drivers, ADCs, DACs, Regulators, Clock Generation and Distribution, DLLs, Custom high-speed digital circuits, CTLE, VGA.
Cooperate with system and architecture team in identifying the optimal circuit solution based on overall cost function
Supervise, coach and provide technical direction to more junior engineers
Supervise and guide layout activities to ensure design accuracy and performance.
Conduct post-silicon testing and validation of analog mixed-signal circuits.
Collaborate with cross-functional teams to ensure successful project execution.
Prepare and maintain detailed documentation of design processes and results.
Participate and lead design reviews to ensure design quality and compliance with project requirements.