Principal Heterogeneous Systems Architect

Emerson•Austin, TX

3d•Hybrid

About The Position

We are seeking a Distinguished Compute Architect to join the CTO Office and lead the conception, prototyping, and evaluation of heterogeneous computing architectures for next‑generation test and measurement systems. This role sits at the intersection of hardware, software, and system architecture, with a mandate to explore how emerging compute paradigms— CPUs, GPUs, FPGAs, accelerators, and custom silicon —can be applied to radically improve performance, latency, determinism, scalability, and energy efficiency in advanced measurement platforms. As a senior technical leader, you will operate with a high degree of autonomy, partnering across research, product development, and software teams to influence long‑term technology direction and near‑term architectural decisions.

Requirements

BS degree (MS or PhD preferred) in Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of professional experience in system, platform, compute architecture or equivalent commensurate with the level of this role.
Deep understanding of heterogeneous computing systems, including: CPUs, GPUs, FPGAs, and hardware accelerators
Memory systems, cache coherence, and high‑speed busses and interconnects
Real‑time and high‑throughput processing constraints
Experience with HW/SW co‑design, including performance modeling and architectural trade studies.
Strong programming experience in one or more of: C/C++, Python, CUDA, OpenCL, SYCL, or HDL (Verilog/VHDL).
Proven ability to translate abstract architectural ideas into prototypes, benchmarks, or validated concepts.
Excellent written and verbal communication skills, with the ability to explain complex ideas across disciplines.
Authorized to work in the United States without sponsorship now and in the future. Individuals with temporary visas such as E, F-1 (including those with OPT or CPT), H-1, H-2, L-1, B, J or TN, or who need sponsorship for work authorization now or in the future, are not eligible for hire.

Nice To Haves

15+ years of experience in system, platform, or compute architecture.
Experience in test and measurement, instrumentation, RF systems, signal processing, or high‑performance data acquisition.
Background in real‑time systems, deterministic latency, or safety‑critical architectures.
Familiarity with FPGA toolchains, high‑level synthesis, or heterogeneous runtime environments.
Exposure to custom silicon, chiplet‑based systems, or advanced packaging.
Experience working in a CTO office, advanced research group, or incubator environment.

Responsibilities

Architectural Innovation: Develop and evaluate novel heterogeneous compute architectures for advanced test and measurement systems, spanning data acquisition, real‑time signal processing, analytics, and control.
Explore architectural tradeoffs across CPUs, GPUs, FPGAs, DSPs, NPUs, and custom accelerators, including memory hierarchies and interconnects.
Translate emerging compute and system technologies into actionable architectural concepts and prototypes.
HW/SW/System Co‑Design: Lead cross‑layer co‑design across hardware, firmware, bus architectures, runtime, operating systems, drivers, and application software.
Define partitioning strategies between host, accelerator, and real‑time domains to meet performance, latency, and determinism requirements.
Influence software abstractions, APIs, and programmability models that enable scalable heterogeneous systems.
Concept Development and Prototyping: Build and validate architectural concepts using modeling, simulation, and hands‑on prototyping.
Evaluate performance, power, cost, and scalability through benchmarks, proof‑of‑concepts, and silicon/software experiments.
Partner with internal labs or external ecosystems to validate feasibility and readiness.
Technology Strategy and Thought Leadership: Contribute to CTO‑level technology roadmaps and long‑range research initiatives.
Track and assess industry, academic, and open‑source developments in heterogeneous computing, accelerators, and system architecture.
Communicate architectural insights clearly to both technical and executive audiences.
Cross‑Functional Collaboration: Work closely with product engineering, R&D, silicon, software, and platform teams to influence future products.
Mentor engineers and architects, raising architectural rigor and system‑level thinking across the organization.