Principal FPGA/ASIC Engineer - Level 3

Northrop Grumman • Gilbert, AZ

119d • $79,300 - $118,900 • Onsite

About The Position

Northrop Grumman's Space Systems Sector has openings for a Principal FPGA/ASIC Engineer – Level 3 to join our team in Gilbert, AZ. This position description does not represent a current opening but may be used to identify candidates with skills and experience for positions within Northrop Grumman that frequently become available. Candidates who express an interest may be considered for future positions at Northrop Grumman. The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our Command and Data Handling (C&DH) products. The ideal candidate will have demonstrated expertise in FPGA/ASIC for space applications.

Requirements

• Bachelor’s degree in a STEM (Science, Technology, Engineering, and Mathematics) discipline with 5+ years of FPGA design (or related) engineering experience OR Master’s degree in a STEM discipline with 3+ years of FPGA design (or related) engineering experience OR Ph.D. in a STEM discipline with 1+ year(s) of FPGA design (or related) engineering experience
• Prior work experience in HDL design for an aerospace environment or space application
• Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place & route, static timing analysis, and power analysis
• Industry experience in FPGA Design, Simulation and V&V
• Must be able and willing to obtain and maintain an active DoD Top Secret clearance

Nice To Haves

• Advance degree in Electrical or Computer Engineering
• Active DoD Top Secret clearance
• Experience with Electronic Design Automation (EDA) Tools (e.g., Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify)
• Implementation of Digital Signal or Image Processing algorithms on FPGAs
• Expertise achieving timing closure on FPGA designs and generating test benches for full functional simulation
• Experience working with or developing test benches using System Verilog and Universal Verification Methodology (UVM)
• Experience debugging down to the hardware level with experience using Signal Generators, Logic Analyzers, Digital Oscilloscopes and Embedded FPGA Debugging tools

Responsibilities

• HDL design for FPGA and/or ASIC applications
• FPGA/ASIC verification via simulation and emulation (lab testing)
• FPGA/ASIC synthesis, timing analysis, and place & route
• FPGA design for space environments or space applications

Benefits

• Medical, Dental & Vision coverage
• 401k
• Educational Assistance
• Life Insurance
• Employee Assistance Programs & Work/Life Solutions
• Paid Time Off
• Health & Wellness Resources
• Employee Discounts
• Flexible Schedules
• Company paid holidays
• paid time off (PTO) for vacation and/or personal business

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: Ph.D. or professional degree