Principal Firmware/Middleware Engineer

Renesas Electronics•Austin, CA

About The Position

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. In this high-impact role, you will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators.

Requirements

Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline.
15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.
Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling.
Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6).
Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.
Strong familiarity with hardware debuggers (JTAG, Lauterbach Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers).

Responsibilities

Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC.
Collaborate heavily with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps.
Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control.
Design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections.
Architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion.
Lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs.
Fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives (e.g., All-Reduce, All-to-All).
Design robust error-handling, telemetry, and fault-isolation micro-architectures (e.g., link degradation fallback, FEC, and error containment).
Implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity.