Principal Engineer

NXP SemiconductorsChandler, AZ

About The Position

Perform semiconductor engineering design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry. Participate in the digital functional verification of NXP’s mixed-signal circuit designs. Responsible for developing the UVM simulation environment (drivers, monitors, checkers, and assertions) and bridge with mixed signal verification. Develop and run digital and top-level simulations according to the verification plan. Collaborate with design leaders to define the IP test specification. Study specification of the device under test and ensure 100% coverage prior tape-out. Create and maintain regression test suites, report bugs, propose solutions and following their resolution, and prepare and hold design verification review.

Requirements

  • Bachelor’s degree in Electrical Engineering, Electronic Engineering, or Computer Engineering (with related variants such as VLSI or Physics), foreign equivalent or related field.
  • Five (5) years of progressive, post baccalaureate experience in job offered, Engineer, Design Engineer, Verification Engineer, or closely related field.
  • ARM processor with multi-processor intraction
  • Serial communication protocol (I2C,SPI,SPMI,UART)
  • SOC Testbench
  • System Verilog
  • UVM Verification
  • GLS simulations and debug features
  • ASIC design verification
  • Regression management and artifact tracking
  • C-based test development
  • SPI interface

Responsibilities

  • Perform semiconductor engineering design, development, and testing for firm products and devices in conjunction with product development for the electronic communications industry.
  • Participate in the digital functional verification of NXP’s mixed-signal circuit designs.
  • Develop the UVM simulation environment (drivers, monitors, checkers, and assertions) and bridge with mixed signal verification.
  • Develop and run digital and top-level simulations according to the verification plan.
  • Collaborate with design leaders to define the IP test specification.
  • Study specification of the device under test and ensure 100% coverage prior tape-out.
  • Create and maintain regression test suites, report bugs, propose solutions and following their resolution.
  • Prepare and hold design verification review.
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