Principal Engineer, RFIC Design

Kyocera International, Inc. (North America) • San Diego, CA

1d • $135,000 - $304,000 • Onsite

About The Position

Join Kyocera International, Inc. We’re hiring a Principal Engineer, RFIC Design at our San Diego, CA location! Join a stable, long-term opportunity where your work matters. We’re hiring a Principal Engineer, RFIC Design to support production and ensure high-quality output in a fast-paced manufacturing setting. The Principal RFIC Design Engineer develops high-performance RF, analog, and mixed-signal SoCs for advanced wireless and sensing products. The role combines hands-on circuit design with module-level technical ownership, cross-functional leadership, and responsibility for delivering production-ready silicon. May bring deep expertise in receiver, transmitter, frequency-synthesizer/LO-generation, analog, or transceiver integration design.

Requirements

• M.S. or Ph.D. in Electrical Engineering or a related field, with at least 10 years of relevant industry experience in analog and mmWave IC design.
• Demonstrated success delivering complex RFIC blocks or modules from architecture and transistor-level design through layout, silicon validation, and production ramp.
• Deep expertise in one or more relevant areas, including receiver design, transmitter design, PLL and frequency-synthesizer design, LO generation and distribution, analog baseband, calibration, power management, or transceiver integration.
• Strong command of RF and analog design concepts, including device physics, noise, linearity, mismatch, feedback, stability, phase noise, modulation impairments, process variation, thermal effects, and reliability.
• Experience designing and reviewing critical circuits such as LNAs, PAs and drivers, mixers, VGAs, filters, op amps, oscillators, PLLs, dividers, phase shifters, detectors, bias circuits, regulators, and calibration loops, as applicable to the candidate's specialty.
• Strong knowledge of CMOS and/or SOI technologies, deep-submicron effects, RF passives and EM structures, RFIC layout, coupling and isolation, power integrity, and design-for-manufacturability.
• Proficiency with Cadence Virtuoso, Spectre, RF simulation, EM extraction, statistical analysis, mixed-signal verification, and physical-verification tools; familiarity with electrothermal and behavioral modeling is preferred.
• Strong laboratory and silicon-debug experience, with the ability to define measurements, interpret results, and correlate bench and ATE data with simulation.
• Proven technical leadership and mentoring skills, including the ability to lead cross-functional reviews, manage technical risk, and drive timely decisions without losing hands-on design depth.
• Excellent analytical, communication, teamwork, and documentation skills; familiarity with applicable wireless, sensing, emissions, and compliance requirements is desirable.

Nice To Haves

• familiarity with electrothermal and behavioral modeling is preferred.
• familiarity with applicable wireless, sensing, emissions, and compliance requirements is desirable.

Responsibilities

• Lead the architecture, design, layout, integration, verification, characterization, and productization of complex RFIC blocks or modules from concept through production ramp.
• Translate system requirements into block and module specifications, establish performance budgets, and make tradeoffs across power, area, noise, linearity, gain, bandwidth, phase noise, stability, calibration, thermal performance, and reliability.
• Perform hands-on design in one or more areas such as receivers, transmitters, PLLs and frequency synthesizers, LO generation and distribution, analog baseband, biasing, power management, calibration, or transceiver integration.
• Drive schematic, post-layout, PVT, Monte Carlo, EM, mixed-signal, electrothermal, and reliability verification; identify technical risks and close performance gaps using simulation and measurement.
• Guide floorplanning and critical layout, including device matching, parasitic control, shielding, isolation, power integrity, passive structures, and physical verification.
• Lead RFIC-package-PCB-antenna co-design and modeling to account for interconnects, coupling, passives, supply integrity, thermal effects, and conducted or over-the-air performance.
• Define silicon characterization and production-test strategies with Test and Product Engineering, including observability, calibration, guard bands, yield analysis, and correlation between simulation, bench measurements, and ATE.
• Lead silicon debug and resolve complex circuit, integration, customer, field, and yield issues in collaboration with Systems, Layout, Package, PCB, Firmware, Software, Applications, Test, and Manufacturing teams.
• Mentor engineers, lead design and data reviews, establish sound engineering practices, and communicate technical decisions, risks, and status to program teams and management.
• Contribute to technology and product roadmaps, design methodology improvements, and the creation and protection of intellectual property.

Benefits

• Competitive pay, benefits, and hours
• 120 hours of vacation accrued per year to start (that's 3 weeks/year for regular 8-hour shifts!)
• 10 Paid Holidays per year
• 401(k) with company match
• Pension
• Medical, dental, and vision insurance
• Flexible Spending Account (FSA)
• Employee Assistance Program
• Flexible schedules
• Tuition reimbursement
• life insurance
• paid leave options
• employer-paid Pension
• 401(k) with both Roth and a healthy company match
• onsite gyms
• walking tracks
• exercise rooms
• employee gardens

What This Job Offers

• Job Type: Full-time
• Career Level: Principal