Principal Engineer, GPU Design Verification (Subsystems)

Samsung Electronics•San Jose, CA

5d•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a Principal GPU Design Verification Engineer – Subsystems, you will lead the verification of one or more GPU subsystems for Samsung’s next-generation mobile GPU. In this high-impact and highly visible technical leadership role, you will define verification strategy and contribute hands-on to validating complex subsystem designs, ensuring functional correctness, performance integrity, and architectural intent. You bring deep expertise in GPU design verification, strong block- and subsystem-level architectural understanding, and a collaborative leadership style that aligns architecture, design, and software teams while supporting concurrent development cycles. You are a domain expert in multiple areas of subsystem-level verification.

Requirements

15+ years of experience with a Bachelor’s degree in Computer Science/Engineering or related field, or 13+ years with a Master’s degree, or 11+ years with a Ph.D.
10+ years of hands-on experience in GPU, CPU, or advanced semiconductor design verification
Deep understanding of computer architecture and GPU subsystem design, including block-level and subsystem-level integration
Strong programming skills in C/C++, Python, Perl, or equivalent.
Deep expertise in SystemVerilog and UVM, including constrained-random testing, functional coverage, and assertions.
Experience with building configurable UVM testbenches for reuse across design hierarchies, ensuring a block-level environment can seamlessly transition into a system-level environment.
Proven track record of achieving multiple first-pass silicon success.
Proven experience driving verification strategy and execution for multiple subsystem blocks and verification closure across interfaces.
Excellent debugging, analytical, and problem-solving skills, with proven ability to identify bottlenecks, propose solutions and guide teams through implementation.
Excellent communication and collaboration skills, with the ability to navigate ambiguity and influence in a fast-paced, global team environment.

Nice To Haves

Knowledge of memory subsystem or coherent interconnects is a plus.
Experience with performance-aware verification or performance profiling.
Hardware modeling or emulation experience.
Demonstrated passion for learning modern graphics architectures and evolving GPU technologies.

Responsibilities

Lead verification strategy and execution for one or more GPU subsystems by developing comprehensive verification plans, defining verification goals, coverage metrics, and sign-off criteria aligned with architectural specifications and integration requirements.
Architect and implement advanced verification environments using SystemVerilog, UVM, and C++.
Design, develop, and maintain scalable verification testbenches using SystemVerilog, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven verification, and assertion-based techniques to validate complex block and subsystem behaviors.
Elevate functional and performance excellence across subsystem coverage.
Advance verification methodologies, tools, and automation to improve efficiency and quality, while creating targeted and scalable test scenarios that stress interactions across multiple blocks, interfaces, and data paths within the subsystem.
Drive complex debug and issue resolution by leading team to analyze failures spanning blocks within a subsystem, identify root causes, and spearhead cross-functional collaboration to ensure verification aligns with architectural intent and system-level integration expectations.
Inspire high performance by mentoring engineers, fostering a culture of ownership and innovation, and enabling mobility across blocks and subsystems to broaden technical depth and grow verification expertise.