Principal Engineer, AMS IP Architecture

Intel•Hillsboro, CA

10d•Hybrid

About The Position

As a Principal Engineer in AMS IP Architecture, you will play a pivotal role in defining and driving next-generation analog and mixed-signal (AMS) IP architectures that shape the future of Intel's product offerings. You will apply your expertise to develop innovative architectures, signal processing algorithms, and calibration techniques to optimize performance, power, and area across a range of applications. By collaborating with cross-functional teams, you will ensure Intel's AMS solutions deliver exceptional results for diverse segments, from high-performance computing to ultra-low power products. This position is part of Intel's cutting-edge architecture and engineering organization. The team is focused on creating industry-leading analog and mixed-signal IPs that enable world-class product solutions. By combining technical innovation with cross-functional collaboration, the group plays a critical role in delivering scalable, high-performance designs that support Intel's broad portfolio of market-leading technologies.

Requirements

M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing
Deep expertise in one or more of the following: SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory including equalization, coding, and noise filtering
Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise
Hands-on work with SerDes transmitter and receiver architectures, equalization techniques such as FFE, DFE, and CTLE, or CDR loop dynamics and jitter tolerance
Ability to correlate models with silicon measurements, debug discrepancies systematically, and update models to reflect real-world behavior

Nice To Haves

Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus

Responsibilities

Architected end-to-end PCIe SerDes models (NRZ/PAM4) in MATLAB/Simulink, capturing complex TX/RX equalization behavior.
Executed 128Gbps+ link simulations to validate protocol specs and mitigate margin risks prior to tapeout.
Designed real-time calibration and adaptation DSP algorithms balancing convergence speed, stability, and power.
Validated simulation models against lab silicon measurements, closing gaps through iterative behavioral updates.
Partnered with analog, digital, and hardware teams on circuit trade-offs, logic design, and lab bringup.
Resolved technical field issues and performed custom link budget analyses for client channel/module configurations.
Evaluated early-stage protocol updates and design specs to guarantee system-level feasibility.