Principal EDA Engineer

Analog Devices•Durham, NC

1d•$159,638 - $239,457•Onsite

About The Position

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. ADI is seeking a Principal EDA Engineer with deep expertise in Calibre-based physical verification, code development, and tapeout support for advanced analog and mixed-signal programs. This role serves as a technical authority for signoff methodology, rule deck implementation, verification flow development, and critical tapeout readiness across multiple projects and process nodes. The engineer in this role will lead the development and optimization of Calibre-driven flows, build code and tools that extend verification capability, and partner closely with design and layout teams to resolve high-impact issues from project setup through final signoff.

Requirements

Expert-level proficiency with Mentor Calibre across DRC, LVS, ERC, PERC, extraction, and signoff flows
Deep hands-on experience writing, debugging, and maintaining SVRF and TVF rule sets for advanced-node verification
Strong experience developing code, scripts, and internal tools that utilize and extend Calibre workflows, including automation, result parsing, analysis, and debug support
Proven experience supporting tapeouts, final verification closure, waiver flows, antenna-related issues, and foundry-facing signoff requirements
Strong experience with TSMC design rules, rule deck integration, and physical verification challenges at nodes such as 16nm, 5nm, and 4nm
Ability to lead resolution of complex backend verification and extraction issues with significant project or schedule impact
Strong understanding of Linux-based EDA environments, compute infrastructure, license usage, and version-controlled design data workflows
Ability to work effectively with analog layout, design, CAD, and project teams in a fast-paced multi-project environment
Strong understanding of analog layout practices, physical verification issues, and signoff expectations

Nice To Haves

BS or MS in Electrical Engineering, Computer Engineering, or a related field, or an equivalent combination of education and 10+ years of related experience
Experience supporting digital physical design or place-and-route verification flows
Experience with Perforce for design data management
Experience with Cadence Virtuoso customization, including SKILL, bindkeys, or layout environment setup
Experience building GUI-based tools, reporting systems, or verification analytics dashboards
Experience with EDA license management, compute optimization, or multi-site verification infrastructure
Familiarity with AI-assisted methods that improve verification productivity, debug efficiency, or flow effectiveness

Responsibilities

Serve as a recognized expert for Calibre-based physical verification flows, including DRC, LVS, ERC, PERC, parasitic extraction, and signoff methodology
Define, develop, maintain, and optimize Calibre verification flows and supporting infrastructure for analog and mixed-signal design teams
Write, debug, and enhance SVRF and TVF rule sets, along with custom code and scripts that extend Calibre capabilities, improve debug efficiency, and strengthen flow reliability
Lead or guide tapeout readiness activities, including final signoff checks, waiver management, antenna-related issue resolution, deliverable preparation, and coordination of critical verification closure items
Drive intake, validation, integration, and versioning of foundry rule files and process updates for advanced-node programs
Resolve the most complex verification, runset, extraction, and rule deck issues affecting project execution or tapeout schedules
Support new project setup, verification environment readiness, and early issue identification so design teams can avoid downstream signoff risk
Build internal tools, scripts, dashboards, and reporting utilities that improve verification visibility, XOR analysis, runtime efficiency, and license or compute usage
Provide training, documentation, and expert guidance to engineers using verification flows and signoff methodologies across the organization