Principal Digital Engineer

Northrop Grumman•Linthicum Heights, MD

1d•Onsite

About The Position

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. At the heart of Defining Possible is our commitment to missions. In rapidly changing global security environments, Northrop Grumman brings informed insights and software-secure technology to enable strategic planning. We’re looking for innovators who can help us keep building on our wide portfolio of secure, affordable, integrated, and multi-domain systems and technologies that fuel those missions. By joining in our shared mission, we’ll support yours of expanding your personal network and developing skills, whether you are new to the field, or an industry thought leader. At Northrop Grumman, you’ll have the resources, support, and team to do some of the best work of your career. We are seeking a front-end ASIC design engineer for architecture, design, and verification of full-custom digital and mixed-signal superconducting circuits. Must be proficient in Verilog, System Verilog or VHDL RTL coding, writing functional test benches, and have a thorough understanding of synchronous digital design concepts. Must be able to create a functional verification plan based on requirements of the circuit. Able to generate manufacturing test vectors and manufacturing test plan. Must be knowledgeable in synthesis, SDC constraints, formal verification, and static timing. Knowledge of scan insertion and ATPG is a plus. Able to interface with place and route engineers for floor planning and clock tree constraints and timing closure. Understanding of power estimation techniques is a plus. Automated place-and-route and physical verification knowledge is a plus. Must have strong written and oral communication skills.

Requirements

Bachelor’s degree with 5 years of experience, master's degree with 3 years of experience or Ph.D. with 1 year of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree.
U.S Citizenship is required.
Ability to obtain/maintain an active U.S. Government Secret Clearance
Experience with full product life cycle (requirements, design, implementation, test) of ASIC designs and architecture
Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
Experience with with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Xcelium, Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus
Strong written and oral communication skills.

Nice To Haves

Advanced degree - either MS or PhD
Current security clearance or eligibility
Knowledge of principles of superconductivity
Experience with chip level integration and ASIC chip lead - Strong design automation skills
Experience in CAD design network, tool configuration, and data management
Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre.
Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints)
Knowledge of scan insertion and ATPG is a plus.
Understanding of power estimation techniques is a plus.
Automated place-and-route and physical verification knowledge is a plus.

Responsibilities

Circuit behavioral coding in Verilog, System Verilog or VHDL RTL
Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools
Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL
Power estimation for superconducting circuits
Generating manufacturing test vectors and manufacturing circuit test plan
Assisting with the development of automated procedures to streamline digital design work flows