Principal DFT Engineer (Silicon Engineering)

SpaceX•Irvine, CA

7d•$200,000 - $285,000

About The Position

SpaceX is seeking a motivated, proactive, and intellectually curious Principal DFT Engineer to work alongside world-class cross-disciplinary teams. In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

Bachelor’s degree in electrical engineering, computer engineering or computer science
10+ years of experience working with ASICs
10+ years of experience in scan insertion and DFT setup, integration and validation

Nice To Haves

Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
Ability to solve complex problems including clock domain crossings and power optimization
Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
Familiar with advanced silicon process and technology nodes for high speed and low power consumption
Strong implementation or integration of design blocks using Verilog/SystemVerilog
Experience working with ATE testers and test teams

Responsibilities

Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
Provide post-silicon testing and validation support
Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Run and debug non-timing and SDF annotated gate level simulations
Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

Benefits

Comprehensive medical, vision, and dental coverage
Access to a 401(k) retirement plan
Short & long-term disability insurance
Life insurance
Paid parental leave
Various other discounts and perks
3 weeks of paid vacation
10 or more paid holidays per year
5 days of sick leave per year (for exempt employees)
Long-term incentives, in the form of company stock, stock options, or long-term cash awards
Potential discretionary bonuses
Ability to purchase additional stock at a discount through an Employee Stock Purchase Plan