Principal Design Verification Engineer |Afshin| SJC/ TDC
Astera Labs•Toronto, ON
•CA$140,000 - CA$175,000
About The Position
Astera Labs is seeking a Technical Lead Design Verification Engineer with extensive experience in all facets of verification using UVM and C/C++. The role requires the candidate to leverage high-level programming languages like C/C++ to interact with System Verilog and/or UVM environments, supporting RTL simulation, CoSimulation, and Emulation.
Requirements
- Strong academic and technical background in electrical engineering.
- Bachelor's degree in EE required; Master's preferred.
- Minimum of 8 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks.
- Ability to plan and prepare for customer meetings in advance.
- Ability to work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude.
- Ability to think and act fast with the customer in mind.
- Authorized to work in Canada and start immediately.
Nice To Haves
- Software debugging for SoC-based designs in the area of kernel/device-drivers/u-boot.
- Physical Layer, Link Layer, and Transaction Layer verification expertise in PCIe protocol.
- Experience in memory technologies like DDR4/DDR5/HBM.
- Experience with FPGA-based verification/emulation.
Responsibilities
- Integrate C/C++ into System Verilog environments using DPI/PLI.
- Utilize scripting tools (Perl/Python) for automating verification infrastructure.
- Develop infrastructure and tests in a hybrid directed and constrained random environment.
- Independently develop test-plans and related test-sequences in UVM to generate stimuli.
- Collaborate with RTL designers to debug failures.
- Develop user-controlled random constraints in a transaction-based verification methodology.
- Write assertions and cover properties, and analyze coverage data.
- Utilize Verification IPs from third-party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc.
- Develop VIP abstraction layers to simplify and scale verification deployments.
Benefits
- Base salary range is $140,000 CAD -$175,000 CAD, determined based on candidate capabilities and employees in similar positions.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
