Principal Design Verification Engineer – CPU Subsystem Power Management

SiFive•Austin, TX

About The Position

SiFive is looking for a Principal Design Verification Engineer to lead verification of CPU-subsystem power-management functionality across complex SoC and subsystem environments, with a strong emphasis on data-center-grade quality, resiliency, and signoff readiness. This is a principal tech-lead role for an engineer who can define architecture-aware verification strategy early, identify integration and microarchitectural risk, solve difficult subsystem-level problems, and raise the quality bar across the broader power-management verification effort. The technical scope spans core, cluster, LLC, and uncore power-management behavior, including DVFS, live retention, clock gating, warm reset, power gating, and subsystem interactions across PMC and related control paths. In this role, you will work closely with architecture, RTL, formal, performance, and design verification teams to ensure design intent is captured correctly, debugability is considered early, and signoff quality is achieved with strong technical judgment and scalable methodology.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
12+ years of relevant experience in CPU, subsystem, SoC, or ASIC functional verification, with depth appropriate for a Principal / T6 role.
Strong experience in CPU-subsystem or SoC power-management verification, including clock/reset behavior, power-state transitions, retention, gating, and multi-domain interactions.
Strong understanding of high-performance CPU subsystem behavior and the verification challenges that arise across core, cluster, cache, and uncore boundaries.
Strong hands-on experience with SystemVerilog-based verification, scalable verification planning, assertions, checkers, coverage strategy, and debug workflows for complex hardware subsystems.
Proven ability to translate architectural intent into an effective verification strategy and execution plan.
Solid software, scripting, and automation skills in Python or similar languages for DV infrastructure and workflow scalability.
Strong technical communication and cross-functional collaboration skills across architecture, RTL, DV, formal, and performance teams.
12+ years relevant experience with Core/CPU functional verification
8+ years direct experience on memory management verification
Deep understand of computer architecture
Seasoned developer using object oriented programing principles

Nice To Haves

Direct experience verifying CPU-subsystem power-management features such as DVFS, power gating, retention, warm reset, and clock-gating behavior across core, cluster, LLC, and uncore domains.
Experience with PMC- or power-controller-centric verification, including unit-level benches and standalone verification flows.
Experience developing or reviewing checkers for live retention, CCidle, tile or cluster live retention, and related PM correctness checks.
Experience with formal verification, power-aware simulation, emulation, or related advanced verification techniques for subsystem-level signoff.
Experience with subsystem integration issues involving resets, clock-domain interactions, coherency-sensitive traffic, and performance-sensitive power-state transitions in high-performance CPU environments.
Demonstrated ability to influence verification methodology and technical direction beyond immediate ownership.
Working on solving verification challenges of memory management units that are being reused across several different generations of the Cores, as well as IO memory management unit. This includes hypervisor, virtualization, and guest virtualization.

Responsibilities

Lead verification planning and execution for CPU-subsystem power-management features from unit and block level through subsystem integration and signoff.
Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for complex power-state transitions, clock/reset sequencing, retention behavior, DVFS scenarios, warm-reset flows, and multi-domain interactions.
Drive verification across multiple bench contexts as appropriate, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
Own high-value stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, reset interactions, wakeup behavior, and activity-monitor correctness.
Partner closely with architecture, RTL, DV, and infrastructure teams to review specifications, reduce ambiguity early, and improve debugability and verification completeness before issues harden late in the program.
Drive efficient failure analysis and root-cause debug across specification, RTL, verification infrastructure, assertions, and stimulus.
Apply the right verification method for the problem, including simulation, formal techniques, power-aware verification, and emulation where appropriate for subsystem-level signoff.
Contribute reusable methodology, automation, and verification infrastructure that improve quality and productivity across the broader power-management DV organization.
Mentor engineers and provide technical leadership across the power-management verification area, especially for difficult subsystem-level debug and closure challenges.
Help define signoff expectations suitable for data-center-grade CPU subsystems, with attention to correctness across power states, reset behaviors, retention flows, and integration boundaries.