Principal Design Engineer

Micron Technology • San Jose, CA

23h • $176,000 - $298,000 • Onsite

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Design Engineer in NVEG, you will lead the development, layout, and optimization of innovative datapath circuits for next-generation NAND flash memory, with AI utilization as a central pillar of how you work! You are expected to apply AI tools every day to accelerate design exploration, layout iteration, verification, and multi-functional communication, and — equally important — to redesign existing engineering workflows so that AI can be inserted where it delivers the highest leverage! You will act as a key technical leader, driving task forces, making architectural decisions to hit aggressive data-rate and power targets, and setting the standard for how an AI-augmented design engineer operates. Beyond individual productivity, you will mentor the team on how to think, plan, and implement in an AI-first environment.

Requirements

• Bachelors or Masters degree in Electrical Engineering or a related field with 8+ years of relevant IC design experience.
• Demonstrated, hands-on use of AI tools (LLM-based assistants, coding copilots, agentic workflows, or ML-based EDA aids) as a routine part of daily engineering work. Candidates must be able to describe concrete examples where AI meaningfully changed their productivity or design outcome.
• Proven track record to redesign or create engineering workflows around AI capabilities — for example, restructuring specs, review flows, or verification pipelines so that AI can operate on them effectively; building custom prompts, scripts, or agents that automate recurring engineering tasks.
• Good knowledge and deep intuitive understanding of high-speed IO circuit performance, power/area optimization, and top-level chip architecture/floorplanning.
• Proven track record in physical design flows, layout optimization, and parasitic extraction.
• Growth mindset toward AI — willingness to continuously learn new tools, retire old habits, and rethink established workflows as AI capability evolves.

Nice To Haves

• Experience building or deploying custom AI agents, LLM pipelines, or ML models targeted at IC design, verification, layout, or silicon debug problems.
• Familiarity with prompt engineering, retrieval-augmented generation (RAG), fine-tuning, or agentic frameworks applied to engineering workflows.
• Experience quantifying the productivity or quality impact of AI driven workflow changes (cycle-time reduction, defect escape reduction, coverage improvement, etc.).
• Experience with DRAM interfaces (e.g., DDR4/5, LPDDR5/6, HBM3/3E/4) or other high-speed industry-standard interfaces.
• Comprehensive understanding of sophisticated CMOS device physics, device reliability mechanisms, BSIM modeling, and CMOS targets for high-speed IO operation.

Responsibilities

• Use AI tools (LLM-based assistants, code and RTL generation, spec parsing, waveform interpretation, layout suggestion engines) as a default part of daily engineering work. Continuously identify tasks where AI can replace, accelerate, or augment manual effort, and embrace new tools rapidly as they emerge.
• Rearchitect existing design, verification, and debug workflows so that AI is a first-class participant, not a bolt-on. This includes restructuring specification documents, simulation setups, review checklists, and hand-off artifacts to be AI-consumable; building prompt libraries, agents, and scripts that automate recurring engineering patterns; and defining new review and sign-off flows that leverage AI-generated analysis.
• Serve as a technical champion for AI adoption within the design team. Evaluate emerging AI tools and frontier models, run pilots, publish internal standard methodologies, and drive team-wide adoption of workflows that measurably reduce cycle time or improve design quality.
• Manage, design, and verify major IO/datapath blocks (input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, wave pipelines) to rigorously meet performance specifications — employing AI-assisted exploration, sizing, and verification wherever it accelerates convergence.
• Collaborate closely with project integration and other functional design teams to define and negotiate block interface specifications. Use AI to summarize discussions, reconcile specs across teams, and surface inconsistencies early.
• Liaise with Applications Engineering (Apps) to evaluate new specifications, balancing customer needs against design and physical constraints. Use AI to accelerate feasibility studies and quantify trade-offs.
• Document AI-augmented methodologies, present final results to expert panels and team members, and mentor new engineers on how to think and work in an AI-first environment — not just which tools to click.

Benefits

• choice of medical, dental and vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• robust paid time-off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Principal