Principal Design Engineer - IP Office

Microsoft•Mountain View, CA

About The Position

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Engineer – IP Office to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. Be a highly motivated self-starter who will thrive in this cutting-edge technical environment. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. #SCHIE

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport.
Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

10+ years of experience in interaction with major IP suppliers, IP selection, QA and Release process, Integration of IPs in major CPU, GPU or AI accelerator SoCs and close interactions with Major IP vendors and suppliers of SoCs
6+ Design experience either in IP development or in SoC level Integration of at least one of the following areas: SRAM design, Register Files and Memory Compilers High Speed serial and/or Parallel IOs Sub-system and SoC integration
5+ years of experience as a leader of IP office functions of a major CPU, GPU or AI SoC
Established reputation in interactions with leading suppliers of IPs in 112G/224G class Ethernet, PCIe 5/6, HBM3/4
Track record of successful tape outs in deep sub-micron technologies
Scripting language such as Python or Perl
Knowledge of Front-end and back-end IP Integration flows in a SoC
Strong communication skills, self-motivation, and ability to collaborate with architecture, Front-end, Physical design and post-silicon teams in Microsoft Silicon Engineering

Responsibilities

Establish yourself as an integral member of AI SoC design team for the development of AI components with focus on best-in-class IP selection, QA and ensuring smooth integration in the SoCs.
Identifying new value-adding, best-in-class IPs in the areas of PLL, DTS, Droop-Detector, HBM4,224 G Ethernet, GPIOs etc
Facilitate selection of the most suitable IPs for targeted SoC landing-zones
Architect robust process for IP release, update, QA, integration and pre/post silicon validations
Track release and updates of the IPs and ensure appropriate integration
Review of the IP integrations, signal and power integrity, package and board designs with experts in Microsoft team as well as team experts and IP vendors.
Ensure quality of incoming IPs and facilitate smooth integrations by working closely with Logic design and Physical design teams.
Interface with architecture, physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and teamwork